| Line 60... |
Line 60... |
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entity charmaps_ROM is
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entity charmaps_ROM is
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port (
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port (
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-- i_DI : in std_logic_vector(7 downto 0); -- 8-bit Data Input
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-- i_DI : in std_logic_vector(7 downto 0); -- 8-bit Data Input
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-- i_DIP : in std_logic; -- 1-bit parity Input
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-- i_DIP : in std_logic; -- 1-bit parity Input
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-- i_EN : in std_logic; -- RAM Enable Input
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-- i_WE : in std_logic; -- Write Enable Input
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-- i_WE : in std_logic; -- Write Enable Input
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-- i_SSR : in std_logic; -- Synchronous Set/Reset Input
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-- i_SSR : in std_logic; -- Synchronous Set/Reset Input
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i_EN : in std_logic; -- RAM Enable Input
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i_clock : in std_logic; -- Clock
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i_clock : in std_logic; -- Clock
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i_ADDR : in std_logic_vector(10 downto 0); -- 11-bit Address Input
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i_ADDR : in std_logic_vector(10 downto 0); -- 11-bit Address Input
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o_DO : out std_logic_vector(7 downto 0) -- 8-bit Data Output
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o_DO : out std_logic_vector(7 downto 0) -- 8-bit Data Output
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-- o_DOP : out std_logic -- 1-bit parity Output
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-- o_DOP : out std_logic -- 1-bit parity Output
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);
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);
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end charmaps_ROM;
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end charmaps_ROM;
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architecture rtl of charmaps_ROM is
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architecture rtl of charmaps_ROM is
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signal s_EN : std_logic;
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begin
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begin
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s_EN <= i_EN;
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-- charmaps
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-- charmaps
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-- |------| |-----------------|
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-- |------| |-----------------|
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-- | P | | D D D D D D D D |
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-- | P | | D D D D D D D D |
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-- |======| |=================|
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-- |======| |=================|
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-- | 8 | | 7 6 5 4 3 2 1 0 |
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-- | 8 | | 7 6 5 4 3 2 1 0 |
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| Line 109... |
Line 110... |
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
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)
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)
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port map(
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port map(
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DI => (others => '1'), -- 8-bit Data Input
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DI => (others => '1'), -- 8-bit Data Input
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DIP => (others => '1'), -- 1-bit parity Input
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DIP => (others => '1'), -- 1-bit parity Input
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EN => '1', -- RAM Enable Input
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EN => s_EN, -- RAM Enable Input
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WE => '0', -- Write Enable Input
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WE => '0', -- Write Enable Input
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SSR => '0', -- Synchronous Set/Reset Input
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SSR => '0', -- Synchronous Set/Reset Input
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CLK => i_clock, -- Clock
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CLK => i_clock, -- Clock
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ADDR => i_ADDR, -- 11-bit Address Input
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ADDR => i_ADDR, -- 11-bit Address Input
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DO => o_DO, -- 8-bit Data Output
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DO => o_DO, -- 8-bit Data Output
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