| Line 60... |
Line 60... |
|
|
entity charmaps_ROM is
|
entity charmaps_ROM is
|
port (
|
port (
|
-- i_DI : in std_logic_vector(7 downto 0); -- 8-bit Data Input
|
-- i_DI : in std_logic_vector(7 downto 0); -- 8-bit Data Input
|
-- i_DIP : in std_logic; -- 1-bit parity Input
|
-- i_DIP : in std_logic; -- 1-bit parity Input
|
-- i_EN : in std_logic; -- RAM Enable Input
|
|
-- i_WE : in std_logic; -- Write Enable Input
|
-- i_WE : in std_logic; -- Write Enable Input
|
-- i_SSR : in std_logic; -- Synchronous Set/Reset Input
|
-- i_SSR : in std_logic; -- Synchronous Set/Reset Input
|
|
i_EN : in std_logic; -- RAM Enable Input
|
i_clock : in std_logic; -- Clock
|
i_clock : in std_logic; -- Clock
|
i_ADDR : in std_logic_vector(10 downto 0); -- 11-bit Address Input
|
i_ADDR : in std_logic_vector(10 downto 0); -- 11-bit Address Input
|
o_DO : out std_logic_vector(7 downto 0) -- 8-bit Data Output
|
o_DO : out std_logic_vector(7 downto 0) -- 8-bit Data Output
|
-- o_DOP : out std_logic -- 1-bit parity Output
|
-- o_DOP : out std_logic -- 1-bit parity Output
|
);
|
);
|
end charmaps_ROM;
|
end charmaps_ROM;
|
|
|
architecture rtl of charmaps_ROM is
|
architecture rtl of charmaps_ROM is
|
|
signal s_EN : std_logic;
|
begin
|
begin
|
|
s_EN <= i_EN;
|
-- charmaps
|
-- charmaps
|
-- |------| |-----------------|
|
-- |------| |-----------------|
|
-- | P | | D D D D D D D D |
|
-- | P | | D D D D D D D D |
|
-- |======| |=================|
|
-- |======| |=================|
|
-- | 8 | | 7 6 5 4 3 2 1 0 |
|
-- | 8 | | 7 6 5 4 3 2 1 0 |
|
| Line 88... |
Line 89... |
generic map (
|
generic map (
|
write_mode => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
write_mode => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
|
INIT => B"000000000", -- Value of output RAM registers at startup
|
INIT => B"000000000", -- Value of output RAM registers at startup
|
SRVAL => B"000000000", -- Ouput value upon SSR assertion
|
SRVAL => B"000000000", -- Ouput value upon SSR assertion
|
--
|
--
|
|
-- START REPLACE HERE THE OUTPUT FROM convert.sh
|
INIT_00 => X"000000FF0000FF0000FF0000FF00000000000000000000000000000000000000",
|
INIT_00 => X"000000FF0000FF0000FF0000FF00000000000000000000000000000000000000",
|
INIT_01 => X"0000242424242424242424242424000000000000FF0000FF0000FF0000FF0000",
|
INIT_01 => X"0000242424242424242424242424000000000000FF0000FF0000FF0000FF0000",
|
INIT_02 => X"0000929292929292929292929292000000004949494949494949494949490000",
|
INIT_02 => X"0000929292929292929292929292000000004949494949494949494949490000",
|
INIT_03 => X"0000AAAAAAAAAAAAAAAAAAAAAAAA000000005555555555555555555555550000",
|
INIT_03 => X"0000AAAAAAAAAAAAAAAAAAAAAAAA000000005555555555555555555555550000",
|
INIT_04 => X"0000F3FCF3FCF3FCF3FCF3FCF3FC00000000FF00FF00FF00FF00FF00FF000000",
|
INIT_04 => X"0000F3FCF3FCF3FCF3FCF3FCF3FC00000000FF00FF00FF00FF00FF00FF000000",
|
| Line 152... |
Line 154... |
INIT_3B => X"0000006C92929292928200000000000000000010284482828282000000000000",
|
INIT_3B => X"0000006C92929292928200000000000000000010284482828282000000000000",
|
INIT_3C => X"0000003008083C42820000000000000000000082443828448200000000000000",
|
INIT_3C => X"0000003008083C42820000000000000000000082443828448200000000000000",
|
INIT_3D => X"00000010202020408040202020100000000000FE40300804FE00000000000000",
|
INIT_3D => X"00000010202020408040202020100000000000FE40300804FE00000000000000",
|
INIT_3E => X"0000001008080804020408080810000000000010101010101010101010100000",
|
INIT_3E => X"0000001008080804020408080810000000000010101010101010101010100000",
|
INIT_3F => X"00000000000000000000000000000000000000000000000C9260000000000000",
|
INIT_3F => X"00000000000000000000000000000000000000000000000C9260000000000000",
|
|
-- STOP REPLACE
|
--
|
--
|
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", -- free
|
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", -- free
|
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
| Line 165... |
Line 168... |
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
|
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
|
)
|
)
|
port map(
|
port map(
|
DI => (others => '1'), -- 8-bit Data Input
|
DI => (others => '1'), -- 8-bit Data Input
|
DIP => (others => '1'), -- 1-bit parity Input
|
DIP => (others => '1'), -- 1-bit parity Input
|
EN => '1', -- RAM Enable Input
|
EN => s_EN, -- RAM Enable Input
|
WE => '0', -- Write Enable Input
|
WE => '0', -- Write Enable Input
|
SSR => '0', -- Synchronous Set/Reset Input
|
SSR => '0', -- Synchronous Set/Reset Input
|
CLK => i_clock, -- Clock
|
CLK => i_clock, -- Clock
|
ADDR => i_ADDR, -- 11-bit Address Input
|
ADDR => i_ADDR, -- 11-bit Address Input
|
DO => o_DO, -- 8-bit Data Output
|
DO => o_DO, -- 8-bit Data Output
|
