Line 60... |
Line 60... |
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entity charmaps_ROM is
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entity charmaps_ROM is
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port (
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port (
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-- i_DI : in std_logic_vector(7 downto 0); -- 8-bit Data Input
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-- i_DI : in std_logic_vector(7 downto 0); -- 8-bit Data Input
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-- i_DIP : in std_logic; -- 1-bit parity Input
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-- i_DIP : in std_logic; -- 1-bit parity Input
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-- i_EN : in std_logic; -- RAM Enable Input
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-- i_WE : in std_logic; -- Write Enable Input
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-- i_WE : in std_logic; -- Write Enable Input
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-- i_SSR : in std_logic; -- Synchronous Set/Reset Input
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-- i_SSR : in std_logic; -- Synchronous Set/Reset Input
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i_EN : in std_logic; -- RAM Enable Input
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i_clock : in std_logic; -- Clock
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i_clock : in std_logic; -- Clock
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i_ADDR : in std_logic_vector(10 downto 0); -- 11-bit Address Input
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i_ADDR : in std_logic_vector(10 downto 0); -- 11-bit Address Input
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o_DO : out std_logic_vector(7 downto 0) -- 8-bit Data Output
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o_DO : out std_logic_vector(7 downto 0) -- 8-bit Data Output
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-- o_DOP : out std_logic -- 1-bit parity Output
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-- o_DOP : out std_logic -- 1-bit parity Output
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);
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);
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end charmaps_ROM;
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end charmaps_ROM;
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architecture rtl of charmaps_ROM is
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architecture rtl of charmaps_ROM is
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signal s_EN : std_logic;
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begin
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begin
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s_EN <= i_EN;
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-- charmaps
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-- charmaps
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-- |------| |-----------------|
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-- |------| |-----------------|
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-- | P | | D D D D D D D D |
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-- | P | | D D D D D D D D |
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-- |======| |=================|
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-- |======| |=================|
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-- | 8 | | 7 6 5 4 3 2 1 0 |
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-- | 8 | | 7 6 5 4 3 2 1 0 |
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Line 88... |
Line 89... |
generic map (
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generic map (
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write_mode => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
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write_mode => "NO_CHANGE", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
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INIT => B"000000000", -- Value of output RAM registers at startup
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INIT => B"000000000", -- Value of output RAM registers at startup
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SRVAL => B"000000000", -- Ouput value upon SSR assertion
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SRVAL => B"000000000", -- Ouput value upon SSR assertion
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--
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--
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-- START REPLACE HERE THE OUTPUT FROM convert.sh
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INIT_00 => X"000000FF0000FF0000FF0000FF00000000000000000000000000000000000000",
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INIT_00 => X"000000FF0000FF0000FF0000FF00000000000000000000000000000000000000",
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INIT_01 => X"0000242424242424242424242424000000000000FF0000FF0000FF0000FF0000",
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INIT_01 => X"0000242424242424242424242424000000000000FF0000FF0000FF0000FF0000",
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INIT_02 => X"0000929292929292929292929292000000004949494949494949494949490000",
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INIT_02 => X"0000929292929292929292929292000000004949494949494949494949490000",
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INIT_03 => X"0000AAAAAAAAAAAAAAAAAAAAAAAA000000005555555555555555555555550000",
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INIT_03 => X"0000AAAAAAAAAAAAAAAAAAAAAAAA000000005555555555555555555555550000",
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INIT_04 => X"0000F3FCF3FCF3FCF3FCF3FCF3FC00000000FF00FF00FF00FF00FF00FF000000",
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INIT_04 => X"0000F3FCF3FCF3FCF3FCF3FCF3FC00000000FF00FF00FF00FF00FF00FF000000",
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Line 152... |
Line 154... |
INIT_3B => X"0000006C92929292928200000000000000000010284482828282000000000000",
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INIT_3B => X"0000006C92929292928200000000000000000010284482828282000000000000",
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INIT_3C => X"0000003008083C42820000000000000000000082443828448200000000000000",
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INIT_3C => X"0000003008083C42820000000000000000000082443828448200000000000000",
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INIT_3D => X"00000010202020408040202020100000000000FE40300804FE00000000000000",
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INIT_3D => X"00000010202020408040202020100000000000FE40300804FE00000000000000",
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INIT_3E => X"0000001008080804020408080810000000000010101010101010101010100000",
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INIT_3E => X"0000001008080804020408080810000000000010101010101010101010100000",
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INIT_3F => X"00000000000000000000000000000000000000000000000C9260000000000000",
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INIT_3F => X"00000000000000000000000000000000000000000000000C9260000000000000",
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-- STOP REPLACE
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--
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--
|
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", -- free
|
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", -- free
|
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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Line 165... |
Line 168... |
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
|
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
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)
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)
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port map(
|
port map(
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DI => (others => '1'), -- 8-bit Data Input
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DI => (others => '1'), -- 8-bit Data Input
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DIP => (others => '1'), -- 1-bit parity Input
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DIP => (others => '1'), -- 1-bit parity Input
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EN => '1', -- RAM Enable Input
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EN => s_EN, -- RAM Enable Input
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WE => '0', -- Write Enable Input
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WE => '0', -- Write Enable Input
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SSR => '0', -- Synchronous Set/Reset Input
|
SSR => '0', -- Synchronous Set/Reset Input
|
CLK => i_clock, -- Clock
|
CLK => i_clock, -- Clock
|
ADDR => i_ADDR, -- 11-bit Address Input
|
ADDR => i_ADDR, -- 11-bit Address Input
|
DO => o_DO, -- 8-bit Data Output
|
DO => o_DO, -- 8-bit Data Output
|