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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use work.yavga_pkg.all;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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library UNISIM;
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library UNISIM;
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use UNISIM.VComponents.all;
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use UNISIM.VComponents.all;
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-- i_DIP : in std_logic; -- 1-bit parity Input
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-- i_DIP : in std_logic; -- 1-bit parity Input
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-- i_WE : in std_logic; -- Write Enable Input
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-- i_WE : in std_logic; -- Write Enable Input
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-- i_SSR : in std_logic; -- Synchronous Set/Reset Input
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-- i_SSR : in std_logic; -- Synchronous Set/Reset Input
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i_EN : in std_logic; -- RAM Enable Input
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i_EN : in std_logic; -- RAM Enable Input
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i_clock : in std_logic; -- Clock
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i_clock : in std_logic; -- Clock
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i_ADDR : in std_logic_vector(10 downto 0); -- 11-bit Address Input
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i_ADDR : in std_logic_vector(c_INTCHMAP_ADDR_BUS_W - 1 downto 0); -- 11-bit Address Input
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o_DO : out std_logic_vector(7 downto 0) -- 8-bit Data Output
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o_DO : out std_logic_vector(c_INTCHMAP_DATA_BUS_W - 1 downto 0) -- 8-bit Data Output
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-- o_DOP : out std_logic -- 1-bit parity Output
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-- o_DOP : out std_logic -- 1-bit parity Output
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);
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);
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end charmaps_ROM;
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end charmaps_ROM;
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architecture rtl of charmaps_ROM is
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architecture rtl of charmaps_ROM is
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