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[/] [yavga/] [trunk/] [vhdl/] [chars_RAM.vhd] - Diff between revs 23 and 28
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| Rev 23 |
Rev 28 |
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Line 51... |
library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use work.yavga_pkg.all;
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-- Uncomment the following lines to use the declarations that are
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-- Uncomment the following lines to use the declarations that are
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-- provided for instantiating Xilinx primitive components.
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-- provided for instantiating Xilinx primitive components.
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library UNISIM;
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library UNISIM;
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use UNISIM.VComponents.all;
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use UNISIM.VComponents.all;
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entity chars_RAM is
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entity chars_RAM is
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port (
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port (
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i_clock_rw : in std_logic; -- Write Clock
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i_clock_rw : in std_logic; -- Write Clock
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i_EN_rw : in std_logic; -- Write RAM Enable Input
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i_EN_rw : in std_logic; -- Write RAM Enable Input
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i_WE_rw : in std_logic_vector(3 downto 0); -- Write Enable Input
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i_WE_rw : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0); -- Write Enable Input
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i_ADDR_rw : in std_logic_vector(10 downto 0); -- Write 11-bit Address Input
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i_ADDR_rw : in std_logic_vector(10 downto 0); -- Write 11-bit Address Input
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i_DI_rw : in std_logic_vector(31 downto 0); -- Write 32-bit Data Input
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i_DI_rw : in std_logic_vector(31 downto 0); -- Write 32-bit Data Input
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o_DI_rw : out std_logic_vector(31 downto 0); -- Write 32-bit Data Input
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o_DI_rw : out std_logic_vector(31 downto 0); -- Write 32-bit Data Input
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i_SSR : in std_logic; -- Synchronous Set/Reset Input
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i_SSR : in std_logic; -- Synchronous Set/Reset Input
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