| Line 70... |
Line 70... |
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component vga_ctrl
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component vga_ctrl
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port(
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port(
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i_clk : in std_logic;
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i_clk : in std_logic;
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i_reset : in std_logic;
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i_reset : in std_logic;
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i_background : in std_logic;
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i_cursor_color : in std_logic_vector(2 downto 0);
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i_cursor_x : in std_logic_vector(10 downto 0);
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i_cursor_y : in std_logic_vector(9 downto 0);
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i_h_sync_en : in std_logic;
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i_h_sync_en : in std_logic;
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i_v_sync_en : in std_logic;
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i_v_sync_en : in std_logic;
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i_chr_addr : in std_logic_vector(10 downto 0);
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i_chr_addr : in std_logic_vector(10 downto 0);
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i_chr_data : in std_logic_vector(31 downto 0);
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i_chr_data : in std_logic_vector(31 downto 0);
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i_chr_clk : in std_logic;
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i_chr_clk : in std_logic;
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i_chr_en : in std_logic;
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i_chr_en : in std_logic;
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i_chr_we : in std_logic_vector(3 downto 0);
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i_chr_we : in std_logic_vector(3 downto 0);
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i_chr_rst : in std_logic;
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i_chr_rst : in std_logic;
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i_wav_d : in std_logic_vector(15 downto 0);
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i_wav_d : in std_logic_vector(15 downto 0);
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i_wav_clk : in std_logic;
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i_wav_we : in std_logic;
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i_wav_we : in std_logic;
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i_wav_addr : in std_logic_vector(9 downto 0);
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i_wav_addr : in std_logic_vector(9 downto 0);
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o_h_sync : out std_logic;
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o_h_sync : out std_logic;
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o_v_sync : out std_logic;
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o_v_sync : out std_logic;
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o_r : out std_logic;
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o_r : out std_logic;
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Line 100... |
signal s_b : std_logic;
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signal s_b : std_logic;
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signal s_vsync_count : std_logic_vector(7 downto 0) := (others => '0');
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signal s_vsync_count : std_logic_vector(7 downto 0) := (others => '0');
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signal s_vsync1 : std_logic;
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signal s_vsync1 : std_logic;
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signal s_chr_addr : std_logic_vector(10 downto 0) := (others => '0');
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signal s_chr_addr : std_logic_vector(10 downto 0);-- := (others => '0');
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signal s_rnd : std_logic_vector(31 downto 0) := (others => '0');
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signal s_chr_data : std_logic_vector(31 downto 0);-- := (others => '0');
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signal s_rnd : std_logic_vector(31 downto 0);-- := (others => '0');
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signal s_chr_we : std_logic_vector(3 downto 0);
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signal s_chr_we : std_logic_vector(3 downto 0);
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signal s_wav_addr : std_logic_vector(9 downto 0);
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signal s_wav_d : std_logic_vector(15 downto 0);
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signal s_mul : std_logic_vector(7 downto 0);
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signal s_initialized : std_logic := '0';
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attribute U_SET : string;
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attribute U_SET : string;
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attribute U_SET of "u1_vga_ctrl" : label is "u1_vga_ctrl_uset";
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attribute U_SET of "u1_vga_ctrl" : label is "u1_vga_ctrl_uset";
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begin
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begin
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o_hsync <= s_hsync;
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o_hsync <= s_hsync;
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Line 124... |
o_b <= s_b;
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o_b <= s_b;
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u1_vga_ctrl : vga_ctrl port map(
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u1_vga_ctrl : vga_ctrl port map(
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i_clk => i_clk,
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i_clk => i_clk,
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i_reset => '0',
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i_reset => '0',
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i_background => '0',
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i_cursor_color => "001",
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i_cursor_x => "00101000000",
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i_cursor_y => "0011000000",
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o_h_sync => s_hsync,
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o_h_sync => s_hsync,
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o_v_sync => s_vsync,
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o_v_sync => s_vsync,
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i_h_sync_en => '1',
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i_h_sync_en => '1',
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i_v_sync_en => '1',
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i_v_sync_en => '1',
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o_r => s_r,
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o_r => s_r,
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o_g => s_g,
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o_g => s_g,
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o_b => s_b,
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o_b => s_b,
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i_chr_addr => s_chr_addr, --B"000_0000_0000",
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i_chr_addr => s_chr_addr, --B"000_0000_0000",
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i_chr_data => s_rnd, --X"00000000",
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i_chr_data => s_chr_data, --X"00000000",
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o_chr_data => open,
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o_chr_data => open,
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i_chr_clk => i_clk,
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i_chr_clk => i_clk,
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i_chr_en => '1',
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i_chr_en => '1',
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i_chr_we => s_chr_we,
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i_chr_we => s_chr_we,
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i_chr_rst => '0',
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i_chr_rst => '0',
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i_wav_d => X"0000", --s_rnd(15 downto 0), --
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i_wav_d => s_wav_d, --X"0000", --s_rnd(15 downto 0), --
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i_wav_we => '0', --s_chr_we(0), --
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i_wav_clk => i_clk,
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i_wav_addr => B"00_0000_0000" --s_chr_addr(9 downto 0) --
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i_wav_we => '0', --'0', -- '1',
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i_wav_addr => s_wav_addr --B"00_0000_0000" --s_chr_addr(9 downto 0) --
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);
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);
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s_wav_addr <= s_rnd(1 downto 0) & s_vsync_count;
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s_mul <= s_vsync_count(3 downto 0) * s_vsync_count(3 downto 0);
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s_wav_d <= B"000" & s_rnd(2 downto 0) & B"00" & s_mul;
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--s_wav_d <= B"000" & "100" & B"00" & s_mul;
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-- s_chr_data <= s_rnd;
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-- p_write_chars : process(i_clk)
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-- begin
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-- if rising_edge(i_clk) then
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-- -- during the sync time in order to avoid flickering
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-- -- and each 128 vsync in order to stop for a while
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-- -- will write random chars...
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-- if s_vsync_count(7) = '1' and (s_hsync = '0' or s_vsync = '0') then
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-- -- generate a pseudo random 32 bit number
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-- s_rnd <= s_rnd(30 downto 0) & (s_rnd(31) xnor s_rnd(21) xnor s_rnd(1) xnor s_rnd(0));
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-- -- increment the address and write enable...
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-- s_chr_addr <= s_chr_addr + 1;
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-- s_chr_we <= "1111";
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-- else
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-- s_chr_addr <= s_chr_addr;
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-- s_chr_we <= "0000";
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-- s_rnd <= s_rnd;
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-- end if;
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-- end if;
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-- end process;
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-- cols cols
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-- 00_01_02_03 ... 96_97_98_99
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-- row_00 "00000000000" ... "00000011000"
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-- row_01 "00000100000" ... "00000111000"
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-- ... ... ...
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-- row_37 "10010100000" ... "10010111000"
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p_write_chars : process(i_clk)
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p_write_chars : process(i_clk)
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begin
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begin
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if rising_edge(i_clk) then
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if rising_edge(i_clk) then
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-- during the sync time in order to avoid flickering
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if s_initialized = '0' then
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-- and each 128 vsync in order to stop for a while
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case s_vsync_count(2 downto 0) is
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-- will write random chars...
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when "000" => -- write ABCD
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if s_vsync_count(7) = '1' and (s_hsync = '0' or s_vsync = '0') then
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s_chr_we <= "1111";
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-- generate a pseudo random 32 bit number
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s_chr_addr <= "00000000000";
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s_rnd <= s_rnd(30 downto 0) & (s_rnd(31) xnor s_rnd(21) xnor s_rnd(1) xnor s_rnd(0));
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s_chr_data <= "01000001" & "01000010" & "01000011" & "01000100";
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-- increment the address and write enable...
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when "001" => -- write EFGH
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s_chr_addr <= s_chr_addr + 1;
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s_chr_we <= "1111";
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s_chr_addr <= "00000011000";
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s_chr_data <= "01000101" & "01000110" & "01000111" & "01001000";
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when "010" => -- write IJKL
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s_chr_we <= "1111";
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s_chr_addr <= "00000100000";
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s_chr_data <= "01001001" & "01001010" & "01001011" & "01001100";
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when "011" => -- write MNOP
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s_chr_we <= "1111";
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s_chr_addr <= "10010100000";
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s_chr_data <= "01001101" & "01001110" & "01001111" & "01010000";
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when "100" => -- write QRST
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s_chr_we <= "1111";
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s_chr_addr <= "10010111000";
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s_chr_data <= "01010001" & "01010010" & "01010011" & "01010100";
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when "101" => -- write config grid and cursor color
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s_chr_we <= "1111";
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s_chr_we <= "1111";
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s_chr_addr <= "00000011011"; -- 108 >> 2
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-- ND bgColor grid,cur ND curs_x curs_y
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s_chr_data <= "00" & "000" & "101" & "000" & "00111000010" & "0101011110";
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-- |--------108-------|-------109-------|----110-----|--111--|
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s_initialized <= '1';
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when others =>
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s_chr_we <= (others => '0');
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s_chr_addr <= (others => '1');
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s_chr_data <= "11111111" & "11111101" & "11111100" & "11111110";
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end case;
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else
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else
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s_chr_addr <= s_chr_addr;
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s_chr_we <= (others => '0');
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s_chr_we <= "0000";
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s_rnd <= s_rnd;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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-- p_rnd_bit : process(i_clk)
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-- p_rnd_bit : process(i_clk)
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