| Line 78... |
Line 78... |
i_v_sync_en : in std_logic;
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i_v_sync_en : in std_logic;
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i_chr_addr : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
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i_chr_addr : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
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i_chr_data : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
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i_chr_data : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
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i_chr_clk : in std_logic;
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i_chr_clk : in std_logic;
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i_chr_en : in std_logic;
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i_chr_en : in std_logic;
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i_chr_we : in std_logic_vector(3 downto 0);
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i_chr_we : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
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i_chr_rst : in std_logic;
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i_chr_rst : in std_logic;
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i_wav_d : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
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i_wav_d : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
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i_wav_clk : in std_logic;
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i_wav_clk : in std_logic;
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i_wav_we : in std_logic;
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i_wav_we : in std_logic;
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i_wav_addr : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
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i_wav_addr : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
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| Line 105... |
Line 105... |
signal s_vsync1 : std_logic;
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signal s_vsync1 : std_logic;
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signal s_chr_addr : std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);-- := (others => '0');
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signal s_chr_addr : std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);-- := (others => '0');
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signal s_chr_data : std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);-- := (others => '0');
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signal s_chr_data : std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);-- := (others => '0');
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signal s_rnd : std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);-- := (others => '0');
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signal s_rnd : std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);-- := (others => '0');
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signal s_chr_we : std_logic_vector(3 downto 0);
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signal s_chr_we : std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
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signal s_wav_addr : std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
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signal s_wav_addr : std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
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signal s_wav_d : std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
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signal s_wav_d : std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
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signal s_mul : std_logic_vector(7 downto 0);
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signal s_mul : std_logic_vector(7 downto 0);
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| Line 204... |
Line 204... |
s_chr_we <= "1111";
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s_chr_we <= "1111";
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s_chr_addr <= "10010111000";
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s_chr_addr <= "10010111000";
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s_chr_data <= "01010001" & "01010010" & "01010011" & "01010100";
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s_chr_data <= "01010001" & "01010010" & "01010011" & "01010100";
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when "101" => -- write config grid and cursor color
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when "101" => -- write config grid and cursor color
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s_chr_we <= "1111";
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s_chr_we <= "1111";
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s_chr_addr <= c_BG_CUR_COLOR_ADDR(c_BG_CUR_COLOR_ADDR'left downto 2); -- c_BG_CUR_COLOR_ADDR >> 2
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s_chr_addr <= c_CFG_BG_CUR_COLOR_ADDR(c_CFG_BG_CUR_COLOR_ADDR'left downto 2); -- c_CFG_BG_CUR_COLOR_ADDR >> 2
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-- ND bgColor grid,cur ND curs_x curs_y
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-- ND bgColor grid,cur ND curs_x curs_y
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s_chr_data <= "00" & "000" & "101" & "000" & "00111000010" & "0101011110";
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s_chr_data <= "00" & "000" & "101" & "000" & "00111000010" & "0101011110";
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-- |--------108-------|-------109-------|----110-----|--111--|
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-- |--------108-------|-------109-------|----110-----|--111--|
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s_initialized <= '1';
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s_initialized <= '1';
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when others =>
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when others =>
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s_chr_we <= (others => '0');
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s_chr_we <= (others => '0');
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s_chr_addr <= (others => '1');
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s_chr_addr <= (others => '1');
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s_chr_data <= "11111111" & "11111101" & "11111100" & "11111110";
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s_chr_data <= "10111110" & "10111101" & "10111100" & "10111011";
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end case;
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end case;
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else
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else
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s_chr_we <= (others => '0');
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s_chr_we <= (others => '0');
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end if;
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end if;
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end if;
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end if;
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