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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use work.yavga_pkg.all;
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---- Uncomment the following library declaration if instantiating
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--library UNISIM;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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o_r : out std_logic;
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o_r : out std_logic;
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o_g : out std_logic;
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o_g : out std_logic;
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o_b : out std_logic;
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o_b : out std_logic;
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-- chars RAM memory
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-- chars RAM memory
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i_chr_addr : in std_logic_vector(10 downto 0);
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i_chr_addr : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
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i_chr_data : in std_logic_vector(31 downto 0);
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i_chr_data : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
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o_chr_data : out std_logic_vector(31 downto 0);
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o_chr_data : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
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i_chr_clk : in std_logic;
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i_chr_clk : in std_logic;
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i_chr_en : in std_logic;
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i_chr_en : in std_logic;
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i_chr_we : in std_logic_vector(3 downto 0);
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i_chr_we : in std_logic_vector(3 downto 0);
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i_chr_rst : in std_logic;
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i_chr_rst : in std_logic;
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-- waveform RAM memory
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-- waveform RAM memory
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i_wav_d : in std_logic_vector(15 downto 0);
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i_wav_d : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
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i_wav_we : in std_logic;
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i_wav_we : in std_logic;
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i_wav_clk : IN std_logic;
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i_wav_clk : IN std_logic;
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i_wav_addr : in std_logic_vector(9 downto 0) --;
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i_wav_addr : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0) --;
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--o_DOA : OUT std_logic_vector(15 downto 0)
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--o_DOA : OUT std_logic_vector(15 downto 0)
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);
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);
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end vga_ctrl;
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end vga_ctrl;
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-- vga timings used
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-- vga timings used
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--Htime: 2.4 1.12 16 1.26 2.4 1.12 usec (h PERIOD = 20.78 usec) Hfreq 48123.195 Hz
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--Htime: 2.4 1.12 16 1.26 2.4 1.12 usec (h PERIOD = 20.78 usec) Hfreq 48123.195 Hz
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--Vtime: 124.68 768.86 12468 477.94 124.68 768.68 usec (v PERIOD = 13839.48 usec) Vfreq 72.257 Hz
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--Vtime: 124.68 768.86 12468 477.94 124.68 768.68 usec (v PERIOD = 13839.48 usec) Vfreq 72.257 Hz
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architecture rtl of vga_ctrl is
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architecture rtl of vga_ctrl is
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constant c_GRID_SIZE : std_logic_vector(6 downto 0) := "1111111";
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constant c_GRID_BIT : integer := 6;
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--
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-- horizontal timing signals (in pixels count )
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constant c_H_DISPLAYpx : integer := 800;
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constant c_H_BACKPORCHpx : integer := 63; -- also 60;
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constant c_H_SYNCTIMEpx : integer := 120;
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constant c_H_FRONTPORCHpx : integer := 56; --also 60;
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constant c_H_PERIODpx : integer := c_H_DISPLAYpx +
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c_H_BACKPORCHpx +
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c_H_SYNCTIMEpx +
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c_H_FRONTPORCHpx;
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--
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-- vertical timing signals (in lines count)
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constant c_V_DISPLAYln : integer := 600;
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constant c_V_BACKPORCHln : integer := 23;
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constant c_V_SYNCTIMEln : integer := 6;
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constant c_V_FRONTPORCHln : integer := 37;
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constant c_V_PERIODln : integer := c_V_DISPLAYln +
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c_V_BACKPORCHln +
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c_V_SYNCTIMEln +
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c_V_FRONTPORCHln;
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-- constant c_CHARS_WIDTH: std_logic_vector(2 downto 0) := "111";
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-- constant c_CHARS_HEIGHT: std_logic_vector(3 downto 0) := "1111";
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-- constant c_CHARS_COLS: std_logic_vector(6 downto 0) := "1100011";
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-- constant c_CHARS_ROWS: std_logic_vector(5 downto 0) := "100100";
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--
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--
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signal s_h_count : std_logic_vector(10 downto 0); -- horizontal pixel counter
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signal s_h_count : std_logic_vector(10 downto 0); -- horizontal pixel counter
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signal s_v_count : std_logic_vector(9 downto 0); -- verticalal line counter
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signal s_v_count : std_logic_vector(9 downto 0); -- verticalal line counter
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signal s_v_count_d_4 : std_logic_vector(3 downto 0); -- verticalal line counter
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signal s_v_count_d_4 : std_logic_vector(3 downto 0); -- verticalal line counter
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signal s_h_sync : std_logic; -- horizontal sync trigger
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signal s_h_sync : std_logic; -- horizontal sync trigger
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signal s_h_sync_pulse : std_logic; -- 1-clock pulse on sync trigger
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signal s_h_sync_pulse : std_logic; -- 1-clock pulse on sync trigger
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--
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--
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-- signals for the charmaps Block RAM component...
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-- signals for the charmaps Block RAM component...
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signal s_charmaps_en : std_logic;
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signal s_charmaps_en : std_logic;
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signal s_charmaps_ADDR : std_logic_vector (10 downto 0);
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signal s_charmaps_ADDR : std_logic_vector (c_INTCHMAP_ADDR_BUS_W - 1 downto 0);
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signal s_charmaps_DO : std_logic_vector (7 downto 0);
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signal s_charmaps_DO : std_logic_vector (c_INTCHMAP_DATA_BUS_W - 1 downto 0);
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--
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--
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-- to manage the outside display region's blanking
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-- to manage the outside display region's blanking
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signal s_display : std_logic;
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signal s_display : std_logic;
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--
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--
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--
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--
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-- to manage the chars ram address and the ram ascii
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-- to manage the chars ram address and the ram ascii
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signal s_chars_ram_addr : std_logic_vector(12 downto 0);
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signal s_chars_ram_addr : std_logic_vector(c_INTCHR_ADDR_BUS_W - 1 downto 0);
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signal s_chars_ascii : std_logic_vector(7 downto 0);
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signal s_chars_ascii : std_logic_vector(c_INTCHR_DATA_BUS_W - 1 downto 0);
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signal s_chars_EN_r : std_logic;
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signal s_chars_EN_r : std_logic;
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-- to manage the waveform ram address and data
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-- to manage the waveform ram address and data
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signal s_waveform_ADDRB : std_logic_vector (9 downto 0);
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signal s_waveform_ADDRB : std_logic_vector (c_WAVFRM_ADDR_BUS_W - 1 downto 0);
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signal s_waveform_DOB : std_logic_vector (15 downto 0);
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signal s_waveform_DOB : std_logic_vector (c_WAVFRM_DATA_BUS_W - 1 downto 0);
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-- charmaps
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-- charmaps
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-- |------| |-----------------|
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-- |------| |-----------------|
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-- | P | | D D D D D D D D |
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-- | P | | D D D D D D D D |
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Line 172... |
--
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--
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component charmaps_rom
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component charmaps_rom
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port(
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port(
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i_EN : in std_logic;
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i_EN : in std_logic;
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i_clock : in std_logic;
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i_clock : in std_logic;
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i_ADDR : in std_logic_vector(10 downto 0); -- 16 x ascii code (W=8 x H=16 pixel)
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i_ADDR : in std_logic_vector(c_INTCHMAP_ADDR_BUS_W - 1 downto 0); -- 16 x ascii code (W=8 x H=16 pixel)
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o_DO : out std_logic_vector(7 downto 0) -- 8 bit char pixel
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o_DO : out std_logic_vector(c_INTCHMAP_DATA_BUS_W - 1 downto 0) -- 8 bit char pixel
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);
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);
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end component;
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end component;
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Line 209... |
component chars_RAM
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component chars_RAM
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port(
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port(
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i_clock_rw : in std_logic;
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i_clock_rw : in std_logic;
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i_EN_rw : in std_logic;
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i_EN_rw : in std_logic;
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i_WE_rw : in std_logic_vector(3 downto 0);
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i_WE_rw : in std_logic_vector(3 downto 0);
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i_ADDR_rw : in std_logic_vector(10 downto 0);
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i_ADDR_rw : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
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i_DI_rw : in std_logic_vector(31 downto 0);
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i_DI_rw : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
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o_DI_rw : out std_logic_vector(31 downto 0);
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o_DI_rw : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
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i_SSR : in std_logic;
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i_SSR : in std_logic;
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i_clock_r : in std_logic;
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i_clock_r : in std_logic;
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i_EN_r : in std_logic;
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i_EN_r : in std_logic;
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i_ADDR_r : in std_logic_vector(12 downto 0);
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i_ADDR_r : in std_logic_vector(c_INTCHR_ADDR_BUS_W - 1 downto 0);
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o_DO_r : out std_logic_vector(7 downto 0)
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o_DO_r : out std_logic_vector(c_INTCHR_DATA_BUS_W - 1 downto 0)
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);
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);
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end component;
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end component;
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attribute U_SET : string;
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attribute U_SET : string;
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-- to read some configuration params from the char ram
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-- to read some configuration params from the char ram
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signal s_config_time : std_logic;
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signal s_config_time : std_logic;
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--
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--
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-- to manage the background and cursor colors
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-- to manage the background and cursor colors
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constant c_BG_CUR_COLOR_ADDR : std_logic_vector(12 downto 0) := "0000001101100"; -- 108 BG:5..3 CUR:2..0
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signal s_cursor_color : std_logic_vector(2 downto 0):= "000";
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signal s_cursor_color : std_logic_vector(2 downto 0):= "000";
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signal s_bg_color : std_logic_vector(2 downto 0):= "000";
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signal s_bg_color : std_logic_vector(2 downto 0):= "000";
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--
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--
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-- to manage the cursor position
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-- to manage the cursor position
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constant c_CURS_XY1 : std_logic_vector(12 downto 0) := "0000001101101"; -- 109
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constant c_CURS_XY2 : std_logic_vector(12 downto 0) := "0000001101110"; -- 110
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constant c_CURS_XY3 : std_logic_vector(12 downto 0) := "0000001101111"; -- 111
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signal s_cursor_x : std_logic_vector(10 downto 0);
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signal s_cursor_x : std_logic_vector(10 downto 0);
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signal s_cursor_y : std_logic_vector(9 downto 0);
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signal s_cursor_y : std_logic_vector(9 downto 0);
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begin
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begin
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-- read config params from ram...
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-- read config params from ram...
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p_config : process(i_clk)
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p_config : process(i_clk)
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begin
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begin
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if rising_edge(i_clk) then
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if rising_edge(i_clk) then
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case s_chars_ram_addr is
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case s_chars_ram_addr is
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when c_BG_CUR_COLOR_ADDR =>
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when c_BG_CUR_COLOR_ADDR => -- bg and curs color are on the same byte byte
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s_config_time <= '1';
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s_config_time <= '1';
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s_cursor_color <= s_chars_ascii(2 downto 0);
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s_cursor_color <= s_chars_ascii(2 downto 0);
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s_bg_color <= s_chars_ascii(5 downto 3);
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s_bg_color <= s_chars_ascii(5 downto 3);
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when c_CURS_XY1 =>
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when c_CURS_XY1 => -- xy coords spans on three bytes
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s_config_time <= '1';
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s_config_time <= '1';
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s_cursor_x(10 downto 6) <= s_chars_ascii(4 downto 0);
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s_cursor_x(10 downto 6) <= s_chars_ascii(4 downto 0);
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when c_CURS_XY2 =>
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when c_CURS_XY2 => -- xy coords spans on three bytes
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s_config_time <= '1';
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s_config_time <= '1';
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s_cursor_x(5 downto 0) <= s_chars_ascii(7 downto 2);
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s_cursor_x(5 downto 0) <= s_chars_ascii(7 downto 2);
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s_cursor_y(9 downto 8) <= s_chars_ascii(1 downto 0);
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s_cursor_y(9 downto 8) <= s_chars_ascii(1 downto 0);
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when c_CURS_XY3 =>
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when c_CURS_XY3 => -- xy coords spans on three bytes
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s_config_time <= '1';
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s_config_time <= '1';
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s_cursor_y(7 downto 0) <= s_chars_ascii(7 downto 0);
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s_cursor_y(7 downto 0) <= s_chars_ascii(7 downto 0);
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when others =>
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when others =>
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s_config_time <= '0';
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s_config_time <= '0';
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end case;
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end case;
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Line 285... |
i_ADDR_r => s_chars_ram_addr,
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i_ADDR_r => s_chars_ram_addr,
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o_DO_r => s_chars_ascii
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o_DO_r => s_chars_ascii
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);
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);
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-- modify the charmaps address (each 8 s_h_count - chars are 8 pixel tall)
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-- modify the charmaps address (each 16 s_v_count - chars are 16 pixel tall)
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-- v----- ascii code ------v v-- vert px mod 16 --v (chars are 8 pixel tall)
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-- v----- ascii code ------v v-- vert px mod 16 --v (chars are 16 pixel tall)
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--s_charmaps_ADDR <= (s_chars_ascii(6 downto 0) & s_v_count(3 downto 0));
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--s_charmaps_ADDR <= (s_chars_ascii(6 downto 0) & s_v_count(3 downto 0));
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s_charmaps_ADDR <= (s_chars_ascii(6 downto 0) & s_v_count_d_4);
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s_charmaps_ADDR <= (s_chars_ascii(6 downto 0) & s_v_count_d_4);
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s_charmaps_en <=
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s_charmaps_en <=
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'1' when s_h_count(2 downto 0) = "111" -- each 8 h_count (chars are 8 pixel wide)
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'1' when s_h_count(2 downto 0) = "111" -- each 8 h_count (chars are 8 pixel wide)
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else '0';
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else '0';
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