| Line 86... |
Line 86... |
i_chr_addr : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
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i_chr_addr : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
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i_chr_data : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
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i_chr_data : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
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o_chr_data : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
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o_chr_data : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
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i_chr_clk : in std_logic;
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i_chr_clk : in std_logic;
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i_chr_en : in std_logic;
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i_chr_en : in std_logic;
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i_chr_we : in std_logic_vector(3 downto 0);
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i_chr_we : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
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i_chr_rst : in std_logic;
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i_chr_rst : in std_logic;
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|
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-- waveform RAM memory
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-- waveform RAM memory
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i_wav_d : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
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i_wav_d : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
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i_wav_we : in std_logic;
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i_wav_we : in std_logic;
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i_wav_clk : IN std_logic;
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i_wav_clk : in std_logic;
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i_wav_addr : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0) --;
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i_wav_addr : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0) --;
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--o_DOA : OUT std_logic_vector(15 downto 0)
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--o_DOA : OUT std_logic_vector(15 downto 0)
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);
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);
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end vga_ctrl;
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end vga_ctrl;
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|
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| Line 131... |
Line 131... |
--Vtime: 124.68 768.86 12468 477.94 124.68 768.68 usec (v PERIOD = 13839.48 usec) Vfreq 72.257 Hz
|
--Vtime: 124.68 768.86 12468 477.94 124.68 768.68 usec (v PERIOD = 13839.48 usec) Vfreq 72.257 Hz
|
|
|
architecture rtl of vga_ctrl is
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architecture rtl of vga_ctrl is
|
|
|
--
|
--
|
signal s_h_count : std_logic_vector(10 downto 0); -- horizontal pixel counter
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signal s_h_count : std_logic_vector(c_H_COUNT_W - 1 downto 0); -- horizontal pixel counter
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signal s_v_count : std_logic_vector(9 downto 0); -- verticalal line counter
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signal s_v_count : std_logic_vector(c_V_COUNT_W - 1 downto 0); -- verticalal line counter
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signal s_v_count_d_4 : std_logic_vector(3 downto 0); -- verticalal line counter
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signal s_v_count_d_4 : std_logic_vector(3 downto 0); -- verticalal line counter mod 16 (char height)
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signal s_h_sync : std_logic; -- horizontal sync trigger
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signal s_h_sync : std_logic; -- horizontal sync trigger
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signal s_h_sync_pulse : std_logic; -- 1-clock pulse on sync trigger
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signal s_h_sync_pulse : std_logic; -- 1-clock pulse on sync trigger
|
|
|
--
|
--
|
-- signals for the charmaps Block RAM component...
|
-- signals for the charmaps Block RAM component...
|
| Line 190... |
Line 190... |
-- | Free | | Reserv. | R G B | vert. pos. |
|
-- | Free | | Reserv. | R G B | vert. pos. |
|
-- |------| |-------------------------------------------|
|
-- |------| |-------------------------------------------|
|
--
|
--
|
component waveform_ram
|
component waveform_ram
|
port(
|
port(
|
i_DIA : in std_logic_vector(15 downto 0);
|
i_DIA : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
|
i_WEA : in std_logic;
|
i_WEA : in std_logic;
|
i_clockA : in std_logic;
|
i_clockA : in std_logic;
|
i_ADDRA : in std_logic_vector(9 downto 0);
|
i_ADDRA : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
|
--o_DOA : OUT std_logic_vector(15 downto 0);
|
--o_DOA : OUT std_logic_vector(15 downto 0);
|
--
|
--
|
i_DIB : in std_logic_vector(15 downto 0);
|
i_DIB : in std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0);
|
i_WEB : in std_logic;
|
i_WEB : in std_logic;
|
i_clockB : in std_logic;
|
i_clockB : in std_logic;
|
i_ADDRB : in std_logic_vector(9 downto 0);
|
i_ADDRB : in std_logic_vector(c_WAVFRM_ADDR_BUS_W - 1 downto 0);
|
o_DOB : out std_logic_vector(15 downto 0)
|
o_DOB : out std_logic_vector(c_WAVFRM_DATA_BUS_W - 1 downto 0)
|
);
|
);
|
end component;
|
end component;
|
|
|
component chars_RAM
|
component chars_RAM
|
port(
|
port(
|
i_clock_rw : in std_logic;
|
i_clock_rw : in std_logic;
|
i_EN_rw : in std_logic;
|
i_EN_rw : in std_logic;
|
i_WE_rw : in std_logic_vector(3 downto 0);
|
i_WE_rw : in std_logic_vector(c_CHR_WE_BUS_W - 1 downto 0);
|
i_ADDR_rw : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
|
i_ADDR_rw : in std_logic_vector(c_CHR_ADDR_BUS_W - 1 downto 0);
|
i_DI_rw : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
|
i_DI_rw : in std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
|
o_DI_rw : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
|
o_DI_rw : out std_logic_vector(c_CHR_DATA_BUS_W - 1 downto 0);
|
i_SSR : in std_logic;
|
i_SSR : in std_logic;
|
i_clock_r : in std_logic;
|
i_clock_r : in std_logic;
|
| Line 234... |
Line 234... |
-- to manage the background and cursor colors
|
-- to manage the background and cursor colors
|
signal s_cursor_color : std_logic_vector(2 downto 0):= "000";
|
signal s_cursor_color : std_logic_vector(2 downto 0):= "000";
|
signal s_bg_color : std_logic_vector(2 downto 0):= "000";
|
signal s_bg_color : std_logic_vector(2 downto 0):= "000";
|
--
|
--
|
-- to manage the cursor position
|
-- to manage the cursor position
|
signal s_cursor_x : std_logic_vector(10 downto 0);
|
signal s_cursor_x : std_logic_vector(c_H_COUNT_W - 1 downto 0);
|
signal s_cursor_y : std_logic_vector(9 downto 0);
|
signal s_cursor_y : std_logic_vector(c_V_COUNT_W - 1 downto 0);
|
|
|
begin
|
begin
|
-- read config params from ram...
|
-- read config params from ram...
|
p_config : process(i_clk)
|
p_config : process(i_clk)
|
begin
|
begin
|
if rising_edge(i_clk) then
|
if rising_edge(i_clk) then
|
case s_chars_ram_addr is
|
case s_chars_ram_addr is
|
when c_BG_CUR_COLOR_ADDR => -- bg and curs color are on the same byte byte
|
when c_CFG_BG_CUR_COLOR_ADDR => -- bg and curs color are on the same byte byte
|
s_config_time <= '1';
|
s_config_time <= '1';
|
s_cursor_color <= s_chars_ascii(2 downto 0);
|
s_cursor_color <= s_chars_ascii(2 downto 0);
|
s_bg_color <= s_chars_ascii(5 downto 3);
|
s_bg_color <= s_chars_ascii(5 downto 3);
|
when c_CURS_XY1 => -- xy coords spans on three bytes
|
when c_CFG_CURS_XY1 => -- xy coords spans on three bytes
|
s_config_time <= '1';
|
s_config_time <= '1';
|
s_cursor_x(10 downto 6) <= s_chars_ascii(4 downto 0);
|
s_cursor_x(10 downto 6) <= s_chars_ascii(4 downto 0);
|
when c_CURS_XY2 => -- xy coords spans on three bytes
|
when c_CFG_CURS_XY2 => -- xy coords spans on three bytes
|
s_config_time <= '1';
|
s_config_time <= '1';
|
s_cursor_x(5 downto 0) <= s_chars_ascii(7 downto 2);
|
s_cursor_x(5 downto 0) <= s_chars_ascii(7 downto 2);
|
s_cursor_y(9 downto 8) <= s_chars_ascii(1 downto 0);
|
s_cursor_y(9 downto 8) <= s_chars_ascii(1 downto 0);
|
when c_CURS_XY3 => -- xy coords spans on three bytes
|
when c_CFG_CURS_XY3 => -- xy coords spans on three bytes
|
s_config_time <= '1';
|
s_config_time <= '1';
|
s_cursor_y(7 downto 0) <= s_chars_ascii(7 downto 0);
|
s_cursor_y(7 downto 0) <= s_chars_ascii(7 downto 0);
|
when others =>
|
when others =>
|
s_config_time <= '0';
|
s_config_time <= '0';
|
end case;
|
end case;
|
