OpenCores
URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [dv/] [la_test2/] [Makefile] - Diff between revs 2 and 22

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 2 Rev 22
Line 23... Line 23...
CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
 
 
## User Project Pointers
## User Project Pointers
UPRJ_VERILOG_PATH ?= ../../../verilog
UPRJ_VERILOG_PATH ?= ../../../verilog
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
UPRJ_BEHAVIOURAL_MODELS = ../
UPRJ_BEHAVIOURAL_MODELS = ../model
 
UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
 
UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
 
 
## RISCV GCC
## RISCV GCC
GCC_PATH?=/ef/apps/bin
GCC_PATH?=/ef/apps/bin
GCC_PREFIX?=riscv32-unknown-elf
GCC_PREFIX?=riscv32-unknown-elf
PDK_PATH?=/ef/tech/SW/sky130A
PDK_PATH?=/ef/tech/SW/sky130A
Line 41... Line 43...
 
 
all:  ${PATTERN:=.vcd}
all:  ${PATTERN:=.vcd}
 
 
hex:  ${PATTERN:=.hex}
hex:  ${PATTERN:=.hex}
 
 
 
vvp:  ${PATTERN:=.vvp}
 
 
%.vvp: %_tb.v %.hex
%.vvp: %_tb.v %.hex
ifeq ($(SIM),RTL)
ifeq ($(SIM),RTL)
        iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
        iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
        -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
        -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
        -I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
        -I $(UPRJ_BEHAVIOURAL_MODELS)    -I $(UPRJ_RTL_PATH) \
 
        -I $(UPRJ_INCLUDE_PATH1)    -I $(UPRJ_INCLUDE_PATH2) \
        $< -o $@
        $< -o $@
else
else
        iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
        iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
        -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
        -I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
        -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \
        -I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH)   -I $(UPRJ_VERILOG_PATH) \

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.