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https://opencores.org/ocsvn/yifive/yifive/trunk
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CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
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CARAVEL_BEHAVIOURAL_MODELS = $(CARAVEL_VERILOG_PATH)/dv/caravel
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## User Project Pointers
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## User Project Pointers
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UPRJ_VERILOG_PATH ?= ../../../verilog
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UPRJ_VERILOG_PATH ?= ../../../verilog
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UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
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UPRJ_RTL_PATH = $(UPRJ_VERILOG_PATH)/rtl
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UPRJ_BEHAVIOURAL_MODELS = ../
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UPRJ_BEHAVIOURAL_MODELS = ../model
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UPRJ_INCLUDE_PATH1 = $(UPRJ_RTL_PATH)/syntacore/scr1/src/includes
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UPRJ_INCLUDE_PATH2 = $(UPRJ_RTL_PATH)/sdram_ctrl/src/defs
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## RISCV GCC
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## RISCV GCC
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GCC_PATH?=/ef/apps/bin
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GCC_PATH?=/ef/apps/bin
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GCC_PREFIX?=riscv32-unknown-elf
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GCC_PREFIX?=riscv32-unknown-elf
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PDK_PATH?=/ef/tech/SW/sky130A
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PDK_PATH?=/ef/tech/SW/sky130A
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all: ${PATTERN:=.vcd}
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all: ${PATTERN:=.vcd}
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hex: ${PATTERN:=.hex}
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hex: ${PATTERN:=.hex}
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vvp: ${PATTERN:=.vvp}
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%.vvp: %_tb.v %.hex
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%.vvp: %_tb.v %.hex
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ifeq ($(SIM),RTL)
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ifeq ($(SIM),RTL)
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iverilog -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
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iverilog -g2005-sv -DFUNCTIONAL -DSIM -I $(PDK_PATH) \
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-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
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-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) \
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-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
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-I $(UPRJ_BEHAVIOURAL_MODELS) -I $(UPRJ_RTL_PATH) \
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-I $(UPRJ_INCLUDE_PATH1) -I $(UPRJ_INCLUDE_PATH2) \
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$< -o $@
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$< -o $@
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else
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else
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iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
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iverilog -DFUNCTIONAL -DSIM -DGL -I $(PDK_PATH) \
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-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
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-I $(CARAVEL_BEHAVIOURAL_MODELS) -I $(CARAVEL_RTL_PATH) -I $(CARAVEL_VERILOG_PATH) \
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-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
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-I $(UPRJ_BEHAVIOURAL_MODELS) -I$(UPRJ_RTL_PATH) -I $(UPRJ_VERILOG_PATH) \
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