| Line 89... |
Line 89... |
sdr_cas_n ,
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sdr_cas_n ,
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sdr_we_n ,
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sdr_we_n ,
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sdr_dqm ,
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sdr_dqm ,
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sdr_ba ,
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sdr_ba ,
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sdr_addr ,
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sdr_addr ,
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sdr_dq ,
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pad_sdr_din ,
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sdr_dout ,
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sdr_den_n ,
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sdram_pad_clk ,
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/* Parameters */
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/* Parameters */
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sdr_init_done ,
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sdr_init_done ,
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cfg_req_depth , //how many req. buffer should hold
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cfg_req_depth , //how many req. buffer should hold
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cfg_sdr_en ,
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cfg_sdr_en ,
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| Line 106... |
Line 109... |
cfg_sdr_twr_d ,
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cfg_sdr_twr_d ,
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cfg_sdr_rfsh ,
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cfg_sdr_rfsh ,
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cfg_sdr_rfmax
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cfg_sdr_rfmax
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);
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);
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parameter APP_AW = 26; // Application Address Width
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parameter APP_AW = 32; // Application Address Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_DW = 32; // Application Data Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_BW = 4; // Application Byte Width
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parameter APP_RW = 9; // Application Request Width
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parameter APP_RW = 9; // Application Request Width
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parameter SDR_DW = 16; // SDR Data Width
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parameter SDR_DW = 8; // SDR Data Width
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parameter SDR_BW = 2; // SDR Byte Width
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parameter SDR_BW = 1; // SDR Byte Width
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parameter dw = 32; // data width
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parameter tw = 8; // tag id width
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parameter tw = 8; // tag id width
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parameter bl = 9; // burst_lenght_width
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parameter bl = 9; // burst_lenght_width
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//-----------------------------------------------
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//-----------------------------------------------
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// Global Variable
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// Global Variable
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| Line 137... |
Line 139... |
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input wb_stb_i ;
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input wb_stb_i ;
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output wb_ack_o ;
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output wb_ack_o ;
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input [APP_AW-1:0] wb_addr_i ;
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input [APP_AW-1:0] wb_addr_i ;
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input wb_we_i ; // 1 - Write, 0 - Read
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input wb_we_i ; // 1 - Write, 0 - Read
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input [dw-1:0] wb_dat_i ;
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input [APP_DW-1:0] wb_dat_i ;
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input [dw/8-1:0] wb_sel_i ; // Byte enable
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input [APP_DW/8-1:0] wb_sel_i ; // Byte enable
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output [dw-1:0] wb_dat_o ;
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output [APP_DW-1:0] wb_dat_o ;
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input wb_cyc_i ;
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input wb_cyc_i ;
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input [2:0] wb_cti_i ;
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input [2:0] wb_cti_i ;
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//------------------------------------------------
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//------------------------------------------------
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// Interface to SDRAMs
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// Interface to SDRAMs
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| Line 154... |
Line 156... |
output sdr_cas_n ; // SDRAM cas
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output sdr_cas_n ; // SDRAM cas
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output sdr_we_n ; // SDRAM write enable
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output sdr_we_n ; // SDRAM write enable
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output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
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output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask
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output [1:0] sdr_ba ; // SDRAM Bank Enable
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output [1:0] sdr_ba ; // SDRAM Bank Enable
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output [12:0] sdr_addr ; // SDRAM Address
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output [12:0] sdr_addr ; // SDRAM Address
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inout [SDR_DW-1:0] sdr_dq ; // SDRA Data Input/output
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input sdram_pad_clk ; // Sdram clock loop back from pad
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input [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
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output [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
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output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
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//------------------------------------------------
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//------------------------------------------------
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// Configuration Parameter
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// Configuration Parameter
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//------------------------------------------------
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//------------------------------------------------
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output sdr_init_done ; // Indicate SDRAM Initialisation Done
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output sdr_init_done ; // Indicate SDRAM Initialisation Done
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| Line 181... |
Line 186... |
wire [APP_AW-1:0] app_req_addr ; // SDRAM Request Address
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wire [APP_AW-1:0] app_req_addr ; // SDRAM Request Address
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wire [bl-1:0] app_req_len ;
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wire [bl-1:0] app_req_len ;
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wire app_req_wr_n ; // 0 - Write, 1 -> Read
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wire app_req_wr_n ; // 0 - Write, 1 -> Read
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wire app_req_ack ; // SDRAM request Accepted
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wire app_req_ack ; // SDRAM request Accepted
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wire app_busy_n ; // 0 -> sdr busy
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wire app_busy_n ; // 0 -> sdr busy
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wire [dw/8-1:0] app_wr_en_n ; // Active low sdr byte-wise write data valid
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wire [APP_DW/8-1:0] app_wr_en_n ; // Active low sdr byte-wise write data valid
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wire app_wr_next_req ; // Ready to accept the next write
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wire app_wr_next_req ; // Ready to accept the next write
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wire app_rd_valid ; // sdr read valid
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wire app_rd_valid ; // sdr read valid
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wire app_last_rd ; // Indicate last Read of Burst Transfer
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wire app_last_rd ; // Indicate last Read of Burst Transfer
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wire app_last_wr ; // Indicate last Write of Burst Transfer
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wire app_last_wr ; // Indicate last Write of Burst Transfer
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wire [dw-1:0] app_wr_data ; // sdr write data
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wire [APP_DW-1:0] app_wr_data ; // sdr write data
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wire [dw-1:0] app_rd_data ; // sdr read data
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wire [APP_DW-1:0] app_rd_data ; // sdr read data
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/****************************************
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/****************************************
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* These logic has to be implemented using Pads
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* These logic has to be implemented using Pads
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* **************************************/
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* **************************************/
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wire [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
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wire [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input
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wire [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
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wire [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output
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wire [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
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wire [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable
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assign sdr_dq = (&sdr_den_n == 1'b0) ? sdr_dout : {SDR_DW{1'bz}};
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//assign sdr_dq = (&sdr_den_n == 1'b0) ? sdr_dout : {SDR_DW{1'bz}};
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assign pad_sdr_din = sdr_dq;
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//assign pad_sdr_din = sdr_dq;
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// sdram pad clock is routed back through pad
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// sdram pad clock is routed back through pad
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// SDRAM Clock from Pad, used for registering Read Data
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// SDRAM Clock from Pad, used for registering Read Data
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wire #(1.0) sdram_pad_clk = sdram_clk;
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//wire #(1.0) sdram_pad_clk = sdram_clk;
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/************** Ends Here **************************/
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/************** Ends Here **************************/
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wb2sdrc #(.dw(dw),.tw(tw),.bl(bl)) u_wb2sdrc (
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wb2sdrc #(.dw(APP_DW),.tw(tw),.bl(bl),.APP_AW(APP_AW)) u_wb2sdrc (
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// WB bus
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// WB bus
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.wb_rst_i (wb_rst_i ) ,
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.wb_rst_i (wb_rst_i ) ,
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.wb_clk_i (wb_clk_i ) ,
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.wb_clk_i (wb_clk_i ) ,
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|
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.wb_stb_i (wb_stb_i ) ,
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.wb_stb_i (wb_stb_i ) ,
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| Line 240... |
Line 245... |
.sdr_rd_data (app_rd_data )
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.sdr_rd_data (app_rd_data )
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|
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);
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);
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sdrc_core #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW)) u_sdrc_core (
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sdrc_core #(.SDR_DW(SDR_DW) , .SDR_BW(SDR_BW),.APP_AW(APP_AW)) u_sdrc_core (
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.clk (sdram_clk ) ,
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.clk (sdram_clk ) ,
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.pad_clk (sdram_pad_clk ) ,
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.pad_clk (sdram_pad_clk ) ,
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.reset_n (sdram_resetn ) ,
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.reset_n (sdram_resetn ) ,
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.sdr_width (cfg_sdr_width ) ,
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.sdr_width (cfg_sdr_width ) ,
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.cfg_colbits (cfg_colbits ) ,
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.cfg_colbits (cfg_colbits ) ,
|
