| Line 70... |
Line 70... |
logic [31:0] data_int;
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logic [31:0] data_int;
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logic [31:0] data_int_next;
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logic [31:0] data_int_next;
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logic [15:0] counter;
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logic [15:0] counter;
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logic [15:0] counter_trgt;
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logic [15:0] counter_trgt;
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logic [15:0] counter_next;
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logic [15:0] counter_next;
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logic [15:0] counter_trgt_next;
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logic reg_done;
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logic reg_done;
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enum logic [1:0] { IDLE, RECEIVE, WAIT_FIFO, WAIT_FIFO_DONE } rx_CS, rx_NS;
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enum logic [1:0] { IDLE, RECEIVE, WAIT_FIFO, WAIT_FIFO_DONE } rx_CS, rx_NS;
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assign reg_done = (!en_quad_in && (counter[4:0] == 5'b11111)) || (en_quad_in && (counter[2:0] == 3'b111));
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assign reg_done = (!en_quad_in && (counter[4:0] == 5'b11111)) || (en_quad_in && (counter[2:0] == 3'b111));
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// RISV is little endian, so data is converted to little endian format
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// RISV is little endian, so data is converted to little endian format
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assign data = (ENDIEAN) ? data_int_next : {data_int_next[7:0],data_int_next[15:8],data_int_next[23:16],data_int_next[31:24]};
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assign data = (ENDIEAN) ? data_int_next : {data_int_next[7:0],data_int_next[15:8],data_int_next[23:16],data_int_next[31:24]};
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assign rx_done = (counter == (counter_trgt-1)) & rx_edge;
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always_comb
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begin
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if (counter_in_upd)
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counter_trgt_next = (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
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else
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counter_trgt_next = counter_trgt;
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end
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always_comb
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always_comb
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begin
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begin
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rx_NS = rx_CS;
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rx_NS = rx_CS;
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clk_en_o = 1'b0;
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data_int_next = data_int;
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data_int_next = data_int;
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data_valid = 1'b0;
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data_valid = 1'b0;
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counter_next = counter;
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counter_next = counter;
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case (rx_CS)
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case (rx_CS)
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IDLE: begin
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IDLE: begin
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clk_en_o = 1'b0;
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// check first if there is available space instead of later
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// check first if there is available space instead of later
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if (en) begin
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if (en) begin
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rx_NS = RECEIVE;
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rx_NS = RECEIVE;
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end
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end
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end
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end
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RECEIVE: begin
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RECEIVE: begin
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clk_en_o = 1'b1;
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if (rx_edge) begin
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if (rx_edge) begin
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counter_next = counter + 1;
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counter_next = counter + 1;
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if (en_quad_in)
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if (en_quad_in)
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data_int_next = {data_int[27:0],sdi3,sdi2,sdi1,sdi0};
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data_int_next = {data_int[27:0],sdi3,sdi2,sdi1,sdi0};
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| Line 130... |
Line 118... |
end else if (reg_done) begin
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end else if (reg_done) begin
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data_valid = 1'b1;
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data_valid = 1'b1;
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if (~data_ready) begin
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if (~data_ready) begin
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// no space in the FIFO, wait for free space
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// no space in the FIFO, wait for free space
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clk_en_o = 1'b0;
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rx_NS = WAIT_FIFO;
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rx_NS = WAIT_FIFO;
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end
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end
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end
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end
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end
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end
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end
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end
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| Line 159... |
Line 146... |
if (rstn == 0)
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if (rstn == 0)
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begin
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begin
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counter <= 0;
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counter <= 0;
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counter_trgt <= 'h8;
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counter_trgt <= 'h8;
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data_int <= '0;
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data_int <= '0;
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rx_done <= '0;
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clk_en_o <= '0;
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rx_CS <= IDLE;
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rx_CS <= IDLE;
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end
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end
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else
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else
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begin
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begin
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if (rx_edge) begin
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counter <= counter_next;
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counter <= counter_next;
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counter_trgt <= counter_trgt_next;
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data_int <= data_int_next;
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data_int <= data_int_next;
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rx_CS <= rx_NS;
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rx_CS <= rx_NS;
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rx_done <= (counter_next == (counter_trgt-1)) && (rx_NS == RECEIVE);
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clk_en_o <= (rx_NS == RECEIVE);
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end
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if (en && counter_in_upd) begin
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counter_trgt <= (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
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end
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end
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end
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end
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end
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endmodule
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endmodule
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