| Line 78... |
Line 78... |
logic tx32b_done ; // 32 bit Transmit done
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logic tx32b_done ; // 32 bit Transmit done
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logic en_quad;
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logic en_quad;
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enum logic [0:0] { IDLE, TRANSMIT } tx_CS, tx_NS;
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enum logic [0:0] { IDLE, TRANSMIT } tx_CS, tx_NS;
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// Counter Exit condition, quad mode div-4 , else actual counter
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always_comb
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begin
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counter_trgt = (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
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end
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//Indicate end of transmission of all the bytes
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assign tx_done = (counter == counter_trgt) && tx_edge;
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// Indicate 32 bit data done, usefull for readining next 32b from txfifo
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// Indicate 32 bit data done, usefull for readining next 32b from txfifo
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assign tx32b_done = (!en_quad && (counter[4:0] == 5'b11111)) || (en_quad && (counter[2:0] == 3'b111)) && tx_edge;
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assign tx32b_done = (!en_quad && (counter[4:0] == 5'b11111)) || (en_quad && (counter[2:0] == 3'b111)) && tx_edge;
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always_comb
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always_comb
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begin
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begin
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tx_NS = tx_CS;
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tx_NS = tx_CS;
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clk_en_o = 1'b0;
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data_int_next = data_int;
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data_int_next = data_int;
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data_ready = 1'b0;
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data_ready = 1'b0;
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counter_next = counter;
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counter_next = counter;
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case (tx_CS)
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case (tx_CS)
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IDLE: begin
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IDLE: begin
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clk_en_o = 1'b0;
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data_int_next = txdata;
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data_int_next = txdata;
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counter_next = '0;
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if (en && data_valid) begin
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if (en && data_valid) begin
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data_ready = 1'b1;
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data_ready = 1'b1;
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tx_NS = TRANSMIT;
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tx_NS = TRANSMIT;
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end
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end
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end
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end
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TRANSMIT: begin
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TRANSMIT: begin
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clk_en_o = 1'b1;
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counter_next = counter + 1;
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counter_next = counter + 1;
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data_int_next = (en_quad) ? {data_int[27:0],4'b0000} : {data_int[30:0],1'b0};
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data_int_next = (en_quad) ? {data_int[27:0],4'b0000} : {data_int[30:0],1'b0};
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if (tx_done) begin
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if (tx_done) begin
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counter_next = 0;
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counter_next = 0;
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| Line 125... |
Line 114... |
if (en && data_valid) begin
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if (en && data_valid) begin
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data_int_next = txdata;
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data_int_next = txdata;
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data_ready = 1'b1;
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data_ready = 1'b1;
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tx_NS = TRANSMIT;
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tx_NS = TRANSMIT;
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end else begin
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end else begin
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clk_en_o = 1'b0;
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tx_NS = IDLE;
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tx_NS = IDLE;
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end
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end
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end else if (tx32b_done) begin
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end else if (tx32b_done) begin
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if (data_valid) begin
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if (data_valid) begin
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data_int_next = txdata;
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data_int_next = txdata;
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data_ready = 1'b1;
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data_ready = 1'b1;
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end else begin
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end else begin
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clk_en_o = 1'b0;
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tx_NS = IDLE;
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tx_NS = IDLE;
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end
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end
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end
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end
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end
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end
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endcase
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endcase
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Line 136... |
begin
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begin
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counter <= 0;
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counter <= 0;
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data_int <= 'h0;
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data_int <= 'h0;
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tx_CS <= IDLE;
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tx_CS <= IDLE;
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en_quad <= 0;
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en_quad <= 0;
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tx_done <= '0;
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clk_en_o <= '0;
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sdo0 <= '0;
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sdo1 <= '0;
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sdo2 <= '0;
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sdo3 <= '0;
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counter_trgt <= '0;
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end
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end
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else
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else
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begin
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begin
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if(tx_edge) begin
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if(tx_edge) begin
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counter <= counter_next;
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counter <= counter_next;
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data_int <= data_int_next;
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data_int <= data_int_next;
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sdo0 <= (en_quad_in) ? data_int_next[28] : data_int_next[31];
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sdo0 <= (en_quad_in) ? data_int_next[28] : data_int_next[31];
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sdo1 <= (en_quad_in) ? data_int_next[29] : 1'b1;
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sdo1 <= (en_quad_in) ? data_int_next[29] : 1'b0;
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sdo2 <= (en_quad_in) ? data_int_next[30] : 1'b1;
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sdo2 <= (en_quad_in) ? data_int_next[30] : 1'b0;
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sdo3 <= (en_quad_in) ? data_int_next[31] : 1'b1;
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sdo3 <= (en_quad_in) ? data_int_next[31] : 1'b0;
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tx_CS <= tx_NS;
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tx_CS <= tx_NS;
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en_quad <= en_quad_in;
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en_quad <= en_quad_in;
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tx_done <= (counter_next == (counter_trgt -1)) && (tx_NS == TRANSMIT);
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clk_en_o <= (tx_NS == TRANSMIT);
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end
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// Counter Exit condition, quad mode div-4 , else actual counter
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if (en && data_valid) begin
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counter_trgt <= (en_quad_in) ? {2'b00,counter_in[15:2]} : counter_in;
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end
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end
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end
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end
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end
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end
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endmodule
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endmodule
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