| Line 78... |
Line 78... |
logic o; // Overflow
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logic o; // Overflow
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logic c; // Carry
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logic c; // Carry
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} type_scr1_ialu_flags_s;
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} type_scr1_ialu_flags_s;
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`ifdef SCR1_RVM_EXT
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`ifdef SCR1_RVM_EXT
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typedef enum logic [1:0] {
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//typedef enum logic [1:0] {
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SCR1_IALU_MDU_FSM_IDLE,
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parameter SCR1_IALU_MDU_FSM_IDLE = 2'b00;
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SCR1_IALU_MDU_FSM_ITER,
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parameter SCR1_IALU_MDU_FSM_ITER = 2'b01;
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SCR1_IALU_MDU_FSM_CORR
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parameter SCR1_IALU_MDU_FSM_CORR = 2'b10;
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} type_scr1_ialu_fsm_state;
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//} type_scr1_ialu_fsm_state;
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typedef enum logic [1:0] {
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//typedef enum logic [1:0] {
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SCR1_IALU_MDU_NONE,
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parameter SCR1_IALU_MDU_NONE = 2'b00;
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SCR1_IALU_MDU_MUL,
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parameter SCR1_IALU_MDU_MUL = 2'b01;
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SCR1_IALU_MDU_DIV
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parameter SCR1_IALU_MDU_DIV = 2'b10;
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} type_scr1_ialu_mdu_cmd;
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//} type_scr1_ialu_mdu_cmd;
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`endif // SCR1_RVM_EXT
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`endif // SCR1_RVM_EXT
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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// Local signals declaration
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// Local signals declaration
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//-------------------------------------------------------------------------------
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//-------------------------------------------------------------------------------
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| Line 121... |
Line 121... |
logic mdu_corr_req; // DIV/REM(U) correction request
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logic mdu_corr_req; // DIV/REM(U) correction request
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logic div_corr_req; // Correction request for DIV operation
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logic div_corr_req; // Correction request for DIV operation
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logic rem_corr_req; // Correction request for REM(U) operations
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logic rem_corr_req; // Correction request for REM(U) operations
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// MUL/DIV FSM signals
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// MUL/DIV FSM signals
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type_scr1_ialu_fsm_state mdu_fsm_ff; // Current FSM state
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logic [1:0] mdu_fsm_ff; // Current FSM state
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type_scr1_ialu_fsm_state mdu_fsm_next; // Next FSM state
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logic [1:0] mdu_fsm_next; // Next FSM state
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logic mdu_fsm_idle; // MDU FSM is in IDLE state
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logic mdu_fsm_idle; // MDU FSM is in IDLE state
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`ifdef SCR1_TRGT_SIMULATION
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`ifdef SCR1_TRGT_SIMULATION
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logic mdu_fsm_iter; // MDU FSM is in ITER state
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logic mdu_fsm_iter; // MDU FSM is in ITER state
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`endif // SCR1_TRGT_SIMULATION
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`endif // SCR1_TRGT_SIMULATION
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logic mdu_fsm_corr; // MDU FSM is in CORR state
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logic mdu_fsm_corr; // MDU FSM is in CORR state
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// MDU command signals
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// MDU command signals
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type_scr1_ialu_mdu_cmd mdu_cmd; // MDU command: 00 - NONE, 01 - MUL, 10 - DIV
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logic [1:0] mdu_cmd; // MDU command: 00 - NONE, 01 - MUL, 10 - DIV
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logic mdu_cmd_mul; // MDU command is MUL(HSU)
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logic mdu_cmd_mul; // MDU command is MUL(HSU)
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logic mdu_cmd_div; // MDU command is DIV(U)/REM(U)
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logic mdu_cmd_div; // MDU command is DIV(U)/REM(U)
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logic [1:0] mul_cmd; // MUL command: 00 - MUL, 01 - MULH, 10 - MULHSU, 11 - MULHU
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logic [1:0] mul_cmd; // MUL command: 00 - MUL, 01 - MULH, 10 - MULHSU, 11 - MULHU
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logic mul_cmd_hi; // High part of MUL result is requested
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logic mul_cmd_hi; // High part of MUL result is requested
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logic [1:0] div_cmd; // DIV command: 00 - DIV, 01 - DIVU, 10 - REM, 11 - REMU
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logic [1:0] div_cmd; // DIV command: 00 - DIV, 01 - DIVU, 10 - REM, 11 - REMU
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