Line 38... |
Line 38... |
input logic pipe2ifu_stop_fetch_i, // Stop instruction fetch
|
input logic pipe2ifu_stop_fetch_i, // Stop instruction fetch
|
|
|
// IFU <-> IMEM interface
|
// IFU <-> IMEM interface
|
input logic imem2ifu_req_ack_i, // Instruction memory request acknowledgement
|
input logic imem2ifu_req_ack_i, // Instruction memory request acknowledgement
|
output logic ifu2imem_req_o, // Instruction memory request
|
output logic ifu2imem_req_o, // Instruction memory request
|
output type_scr1_mem_cmd_e ifu2imem_cmd_o, // Instruction memory command (READ/WRITE)
|
output logic ifu2imem_cmd_o, // Instruction memory command (READ/WRITE)
|
output logic [`SCR1_IMEM_AWIDTH-1:0] ifu2imem_addr_o, // Instruction memory address
|
output logic [`SCR1_IMEM_AWIDTH-1:0] ifu2imem_addr_o, // Instruction memory address
|
input logic [`SCR1_IMEM_DWIDTH-1:0] imem2ifu_rdata_i, // Instruction memory read data
|
input logic [`SCR1_IMEM_DWIDTH-1:0] imem2ifu_rdata_i, // Instruction memory read data
|
input type_scr1_mem_resp_e imem2ifu_resp_i, // Instruction memory response
|
input logic [1:0] imem2ifu_resp_i, // Instruction memory response
|
|
|
// IFU <-> EXU New PC interface
|
// IFU <-> EXU New PC interface
|
input logic exu2ifu_pc_new_req_i, // New PC request (jumps, branches, traps etc)
|
input logic exu2ifu_pc_new_req_i, // New PC request (jumps, branches, traps etc)
|
input logic [`SCR1_XLEN-1:0] exu2ifu_pc_new_i, // New PC
|
input logic [`SCR1_XLEN-1:0] exu2ifu_pc_new_i, // New PC
|
|
|
Line 86... |
Line 86... |
|
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
// Local types declaration
|
// Local types declaration
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
|
|
typedef enum logic {
|
//typedef enum logic {
|
SCR1_IFU_FSM_IDLE,
|
parameter SCR1_IFU_FSM_IDLE = 1'b0;
|
SCR1_IFU_FSM_FETCH
|
parameter SCR1_IFU_FSM_FETCH = 1'b1;
|
} type_scr1_ifu_fsm_e;
|
//} type_scr1_ifu_fsm_e;
|
|
|
typedef enum logic[1:0] {
|
//typedef enum logic[1:0] {
|
SCR1_IFU_QUEUE_WR_NONE, // No write to queue
|
parameter SCR1_IFU_QUEUE_WR_NONE = 2'b00; // No write to queue
|
SCR1_IFU_QUEUE_WR_FULL, // Write 32 rdata bits to queue
|
parameter SCR1_IFU_QUEUE_WR_FULL = 2'b01; // Write 32 rdata bits to queue
|
SCR1_IFU_QUEUE_WR_HI // Write 16 upper rdata bits to queue
|
parameter SCR1_IFU_QUEUE_WR_HI = 2'b10; // Write 16 upper rdata bits to queue
|
} type_scr1_ifu_queue_wr_e;
|
//} type_scr1_ifu_queue_wr_e;
|
|
|
typedef enum logic[1:0] {
|
//typedef enum logic[1:0] {
|
SCR1_IFU_QUEUE_RD_NONE, // No queue read
|
parameter SCR1_IFU_QUEUE_RD_NONE = 2'b00; // No queue read
|
SCR1_IFU_QUEUE_RD_HWORD, // Read halfword
|
parameter SCR1_IFU_QUEUE_RD_HWORD = 2'b01; // Read halfword
|
SCR1_IFU_QUEUE_RD_WORD // Read word
|
parameter SCR1_IFU_QUEUE_RD_WORD = 2'b10; // Read word
|
} type_scr1_ifu_queue_rd_e;
|
//} type_scr1_ifu_queue_rd_e;
|
|
|
`ifdef SCR1_NO_DEC_STAGE
|
`ifdef SCR1_NO_DEC_STAGE
|
typedef enum logic[1:0] {
|
typedef enum logic[1:0] {
|
SCR1_BYPASS_NONE, // No bypass
|
SCR1_BYPASS_NONE, // No bypass
|
SCR1_BYPASS_RVC, // Bypass RVC
|
SCR1_BYPASS_RVC, // Bypass RVC
|
SCR1_BYPASS_RVI_RDATA_QUEUE, // Bypass RVI, rdata+queue
|
SCR1_BYPASS_RVI_RDATA_QUEUE, // Bypass RVI, rdata+queue
|
SCR1_BYPASS_RVI_RDATA // Bypass RVI, rdata only
|
SCR1_BYPASS_RVI_RDATA // Bypass RVI, rdata only
|
} type_scr1_bypass_e;
|
} type_scr1_bypass_e;
|
`endif // SCR1_NO_DEC_STAGE
|
`endif // SCR1_NO_DEC_STAGE
|
|
|
typedef enum logic [2:0] {
|
//typedef enum logic [2:0] {
|
// SCR1_IFU_INSTR__
|
// SCR1_IFU_INSTR__
|
SCR1_IFU_INSTR_NONE, // No valid instruction
|
parameter SCR1_IFU_INSTR_NONE = 3'b000 ; // No valid instruction
|
SCR1_IFU_INSTR_RVI_HI_RVI_LO, // Full RV32I instruction
|
parameter SCR1_IFU_INSTR_RVI_HI_RVI_LO = 3'b001 ; // Full RV32I instruction
|
SCR1_IFU_INSTR_RVC_RVC,
|
parameter SCR1_IFU_INSTR_RVC_RVC = 3'b010 ;
|
SCR1_IFU_INSTR_RVI_LO_RVC,
|
parameter SCR1_IFU_INSTR_RVI_LO_RVC = 3'b011 ;
|
SCR1_IFU_INSTR_RVC_RVI_HI,
|
parameter SCR1_IFU_INSTR_RVC_RVI_HI = 3'b100 ;
|
SCR1_IFU_INSTR_RVI_LO_RVI_HI,
|
parameter SCR1_IFU_INSTR_RVI_LO_RVI_HI = 3'b101 ;
|
SCR1_IFU_INSTR_RVC_NV, // Instruction after unaligned new_pc
|
parameter SCR1_IFU_INSTR_RVC_NV = 3'b110 ; // Instruction after unaligned new_pc
|
SCR1_IFU_INSTR_RVI_LO_NV // Instruction after unaligned new_pc
|
parameter SCR1_IFU_INSTR_RVI_LO_NV = 3'b111 ; // Instruction after unaligned new_pc
|
} type_scr1_ifu_instr_e;
|
//} type_scr1_ifu_instr_e;
|
|
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
// Local signals declaration
|
// Local signals declaration
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
|
|
Line 139... |
Line 139... |
logic new_pc_unaligned_upd;
|
logic new_pc_unaligned_upd;
|
|
|
// IMEM instruction type decoder
|
// IMEM instruction type decoder
|
logic instr_hi_is_rvi;
|
logic instr_hi_is_rvi;
|
logic instr_lo_is_rvi;
|
logic instr_lo_is_rvi;
|
type_scr1_ifu_instr_e instr_type;
|
logic [2:0] instr_type;
|
|
|
// Register to store if the previous IMEM instruction had low part of RVI instruction
|
// Register to store if the previous IMEM instruction had low part of RVI instruction
|
// in its high part
|
// in its high part
|
logic instr_hi_rvi_lo_ff;
|
logic instr_hi_rvi_lo_ff;
|
logic instr_hi_rvi_lo_next;
|
logic instr_hi_rvi_lo_next;
|
|
|
// Queue read/write size decoders
|
// Queue read/write size decoders
|
type_scr1_ifu_queue_rd_e q_rd_size;
|
logic [1:0] q_rd_size;
|
logic q_rd_vd;
|
logic q_rd_vd;
|
logic q_rd_none;
|
logic q_rd_none;
|
logic q_rd_hword;
|
logic q_rd_hword;
|
type_scr1_ifu_queue_wr_e q_wr_size;
|
logic [1:0] q_wr_size;
|
logic q_wr_none;
|
logic q_wr_none;
|
logic q_wr_full;
|
logic q_wr_full;
|
|
|
// Write/read pointer registers
|
// Write/read pointer registers
|
logic [SCR1_IFU_QUEUE_PTR_W-1:0] q_rptr;
|
logic [SCR1_IFU_QUEUE_PTR_W-1:0] q_rptr;
|
Line 194... |
Line 194... |
|
|
// IFU FSM control signals
|
// IFU FSM control signals
|
logic ifu_fetch_req;
|
logic ifu_fetch_req;
|
logic ifu_stop_req;
|
logic ifu_stop_req;
|
|
|
type_scr1_ifu_fsm_e ifu_fsm_curr;
|
logic ifu_fsm_curr;
|
type_scr1_ifu_fsm_e ifu_fsm_next;
|
logic ifu_fsm_next;
|
logic ifu_fsm_fetch;
|
logic ifu_fsm_fetch;
|
|
|
// IMEM signals
|
// IMEM signals
|
//------------------------------------------------------------------------------
|
//------------------------------------------------------------------------------
|
|
|