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Line 16... |
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// MPRF
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// MPRF
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`ifdef SCR1_MPRF_RAM
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`ifdef SCR1_MPRF_RAM
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input logic [`SCR1_XLEN-1:0] mprf2trace_int_i [1:`SCR1_MPRF_SIZE-1], // MPRF registers content
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input logic [`SCR1_XLEN-1:0] mprf2trace_int_i [1:`SCR1_MPRF_SIZE-1], // MPRF registers content
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`else // SCR1_MPRF_RAM
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`else // SCR1_MPRF_RAM
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input type_scr1_mprf_v [1:`SCR1_MPRF_SIZE-1] mprf2trace_int_i, // MPRF registers content
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logic [`SCR1_XLEN-1:0] mprf2trace_int_i[1:`SCR1_MPRF_SIZE-1], // MPRF registers content
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`endif // SCR1_MPRF_RAM
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`endif // SCR1_MPRF_RAM
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input logic mprf2trace_wr_en_i, // MPRF write enable
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input logic mprf2trace_wr_en_i, // MPRF write enable
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input logic [`SCR1_MPRF_AWIDTH-1:0] mprf2trace_wr_addr_i, // MPRF write address
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input logic [`SCR1_MPRF_AWIDTH-1:0] mprf2trace_wr_addr_i, // MPRF write address
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input logic [`SCR1_XLEN-1:0] mprf2trace_wr_data_i, // MPRF write data
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input logic [`SCR1_XLEN-1:0] mprf2trace_wr_data_i, // MPRF write data
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Line 46... |
input logic [`SCR1_XLEN-1:1] csr2trace_mepc_i, // CSR MEPC register
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input logic [`SCR1_XLEN-1:1] csr2trace_mepc_i, // CSR MEPC register
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`else // SCR1_RVC_EXT
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`else // SCR1_RVC_EXT
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input logic [`SCR1_XLEN-1:2] csr2trace_mepc_i, // CSR MEPC register
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input logic [`SCR1_XLEN-1:2] csr2trace_mepc_i, // CSR MEPC register
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`endif // SCR1_RVC_EXT
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`endif // SCR1_RVC_EXT
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input logic csr2trace_mcause_irq_i, // CSR MCAUSE.interrupt bit
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input logic csr2trace_mcause_irq_i, // CSR MCAUSE.interrupt bit
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input type_scr1_exc_code_e csr2trace_mcause_ec_i, // CSR MCAUSE.exception_code bit
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input [SCR1_EXC_CODE_WIDTH_E-1:0] csr2trace_mcause_ec_i, // CSR MCAUSE.exception_code bit
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input logic [`SCR1_XLEN-1:0] csr2trace_mtval_i, // CSR MTVAL register
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input logic [`SCR1_XLEN-1:0] csr2trace_mtval_i, // CSR MTVAL register
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input logic csr2trace_mstatus_mie_up_i, // CSR MSTATUS.mie update flag
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input logic csr2trace_mstatus_mie_up_i, // CSR MSTATUS.mie update flag
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// Events
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// Events
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input logic csr2trace_e_exc_i, // exception event
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input logic csr2trace_e_exc_i, // exception event
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Line 428... |
`ifdef SCR1_RVC_EXT
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`ifdef SCR1_RVC_EXT
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{csr2trace_mepc_i, 1'b0};
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{csr2trace_mepc_i, 1'b0};
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`else // SCR1_RVC_EXT
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`else // SCR1_RVC_EXT
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{csr2trace_mepc_i, 2'b00};
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{csr2trace_mepc_i, 2'b00};
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`endif // SCR1_RVC_EXT
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`endif // SCR1_RVC_EXT
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csr_trace1.mcause = {csr2trace_mcause_irq_i, type_scr1_csr_mcause_ec_v'(csr2trace_mcause_ec_i)};
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csr_trace1.mcause = {csr2trace_mcause_irq_i, csr2trace_mcause_ec_i};
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csr_trace1.mtval = csr2trace_mtval_i;
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csr_trace1.mtval = csr2trace_mtval_i;
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csr_trace1.mstatus = '0;
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csr_trace1.mstatus = '0;
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csr_trace1.mie = '0;
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csr_trace1.mie = '0;
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csr_trace1.mip = '0;
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csr_trace1.mip = '0;
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