URL https://opencores.org/ocsvn/yifive/yifive/trunk

Subversion Repositories yifive

[/] [yifive/] [trunk/] [caravel_yifive/] [verilog/] [rtl/] [syntacore/] [scr1/] [src/] [top/] [scr1_dmem_wb.sv] - Diff between revs 11 and 19

Rev 11	Rev 19
Line 337...	Line 337...


`wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_din = {hbel_in,hwrite_in,hwidth_in,haddr_in,hwdata_in};`	`wire [SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+4:0] req_fifo_din = {hbel_in,hwrite_in,hwidth_in,haddr_in,hwdata_in};`

`sync_fifo #(`	`sync_fifo #(`
`.DATA_WIDTH(SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+1+4), // Data Width`	`.W(SCR1_WB_WIDTH+SCR1_WB_WIDTH+3+1+4), // Data Width`
`.ADDR_WIDTH(1), // Address Width`	`.D(2) // FIFO DEPTH`
`.FIFO_DEPTH(2) // FIFO DEPTH`
`) u_req_fifo(`	`) u_req_fifo(`

`.dout (req_fifo_dout ),`	`.rd_data (req_fifo_dout ),`

`.rstn (rst_n ),`	`.reset_n (rst_n ),`
`.clk (clk ),`	`.clk (clk ),`
`.wr_en (req_fifo_wr ), // Write`	`.wr_en (req_fifo_wr ), // Write`
`.rd_en (req_fifo_rd ), // Read`	`.rd_en (req_fifo_rd ), // Read`
`.din (req_fifo_din ),`	`.wr_data (req_fifo_din ),`
`.full (req_fifo_full ),`	`.full (req_fifo_full ),`
`.empty (req_fifo_empty )`	`.empty (req_fifo_empty )`
`);`	`);`

`//-------------------------------------------------------------------------------`	`//-------------------------------------------------------------------------------`