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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : ////
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//// Revision : ////
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//// v0: June 7, 2021, Dinesh A ////
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//// v0: June 7, 2021, Dinesh A ////
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//// wishbone integration ////
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//// wishbone integration ////
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//// v1: June 9, 2021, Dinesh A ////
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//// On power up, wishbone output are unkown as it ////
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//// driven from fifo output. To avoid unknown ////
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//// propgation, we are driving 'h0 when fifo empty ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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// Core Interface
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// Core Interface
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output logic imem_req_ack,
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output logic imem_req_ack,
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input logic imem_req,
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input logic imem_req,
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input logic [SCR1_WB_WIDTH-1:0] imem_addr,
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input logic [SCR1_WB_WIDTH-1:0] imem_addr,
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output logic [SCR1_WB_WIDTH-1:0] imem_rdata,
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output logic [SCR1_WB_WIDTH-1:0] imem_rdata,
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output type_scr1_mem_resp_e imem_resp,
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output logic [1:0] imem_resp,
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// WB Interface
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// WB Interface
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output logic wbd_stb_o, // strobe/request
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output logic wbd_stb_o, // strobe/request
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output logic [SCR1_WB_WIDTH-1:0] wbd_adr_o, // address
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output logic [SCR1_WB_WIDTH-1:0] wbd_adr_o, // address
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output logic wbd_we_o, // write
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output logic wbd_we_o, // write
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resp_fifo.hrdata <= wbd_dat_i;
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resp_fifo.hrdata <= wbd_dat_i;
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end
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end
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end
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end
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assign wbd_stb_o = ~req_fifo_empty;
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assign wbd_stb_o = ~req_fifo_empty;
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assign wbd_adr_o = req_fifo_dout;
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// On Power, to avoid unknow propgating the value
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assign wbd_adr_o = (req_fifo_empty) ? 'h0 : req_fifo_dout;
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assign wbd_we_o = 0; // Only Read supported
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assign wbd_we_o = 0; // Only Read supported
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assign wbd_dat_o = 32'h0; // No Write
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assign wbd_dat_o = 32'h0; // No Write
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assign wbd_sel_o = 4'b1111; // Only Read allowed in imem i/f
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assign wbd_sel_o = 4'b1111; // Only Read allowed in imem i/f
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`endif // SCR1_IMEM_WB_IN_BP
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`endif // SCR1_IMEM_WB_IN_BP
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