| Line 21... |
Line 21... |
input logic axi_reinit,
|
input logic axi_reinit,
|
// Core Interface
|
// Core Interface
|
output logic core_idle,
|
output logic core_idle,
|
output logic core_req_ack,
|
output logic core_req_ack,
|
input logic core_req,
|
input logic core_req,
|
input type_scr1_mem_cmd_e core_cmd,
|
input logic core_cmd,
|
input type_scr1_mem_width_e core_width,
|
input logic [1:0] core_width,
|
input logic [SCR1_ADDR_WIDTH-1:0] core_addr,
|
input logic [SCR1_ADDR_WIDTH-1:0] core_addr,
|
input logic [31:0] core_wdata,
|
input logic [31:0] core_wdata,
|
output logic [31:0] core_rdata,
|
output logic [31:0] core_rdata,
|
output type_scr1_mem_resp_e core_resp,
|
output logic [1:0] core_resp,
|
|
|
// AXI
|
// AXI
|
output logic [SCR1_AXI_IDWIDTH-1:0] awid,
|
output logic [SCR1_AXI_IDWIDTH-1:0] awid,
|
output logic [SCR1_ADDR_WIDTH-1:0] awaddr,
|
output logic [SCR1_ADDR_WIDTH-1:0] awaddr,
|
output logic [ 7:0] awlen,
|
output logic [ 7:0] awlen,
|
| Line 78... |
Line 78... |
);
|
);
|
|
|
|
|
// Local functions
|
// Local functions
|
function automatic logic [2:0] width2axsize (
|
function automatic logic [2:0] width2axsize (
|
input type_scr1_mem_width_e width );
|
input logic [1:0] width );
|
logic [2:0] axsize;
|
logic [2:0] axsize;
|
begin
|
begin
|
case (width)
|
case (width)
|
SCR1_MEM_WIDTH_BYTE : axsize = 3'b000;
|
SCR1_MEM_WIDTH_BYTE : axsize = 3'b000;
|
SCR1_MEM_WIDTH_HWORD: axsize = 3'b001;
|
SCR1_MEM_WIDTH_HWORD: axsize = 3'b001;
|
| Line 93... |
Line 93... |
width2axsize = axsize; // cp.11
|
width2axsize = axsize; // cp.11
|
end
|
end
|
endfunction
|
endfunction
|
|
|
typedef struct packed {
|
typedef struct packed {
|
type_scr1_mem_width_e axi_width;
|
logic [1:0] axi_width;
|
logic [SCR1_ADDR_WIDTH-1:0] axi_addr;
|
logic [SCR1_ADDR_WIDTH-1:0] axi_addr;
|
logic [31:0] axi_wdata;
|
logic [31:0] axi_wdata;
|
} type_scr1_request_s;
|
} type_scr1_request_s;
|
|
|
typedef struct packed {
|
typedef struct packed {
|
| Line 127... |
Line 127... |
logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_aval_ptr;
|
logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_aval_ptr;
|
logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_proc_ptr;
|
logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_proc_ptr;
|
logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_done_ptr;
|
logic [$clog2(SCR1_REQ_BUF_SIZE)-1:0] req_done_ptr;
|
logic rresp_err;
|
logic rresp_err;
|
logic [31:0] rcvd_rdata;
|
logic [31:0] rcvd_rdata;
|
type_scr1_mem_resp_e rcvd_resp;
|
logic [1:0] rcvd_resp;
|
logic force_read;
|
logic force_read;
|
logic force_write;
|
logic force_write;
|
|
|
|
|
|
|
| Line 306... |
Line 306... |
|
|
|
|
assign wdata = (force_write)? core_wdata << (8* core_addr[1:0]) :
|
assign wdata = (force_write)? core_wdata << (8* core_addr[1:0]) :
|
req_fifo_axi_wdata[req_proc_ptr] << (8* bShift1);
|
req_fifo_axi_wdata[req_proc_ptr] << (8* bShift1);
|
|
|
|
wire [SCR1_ADDR_WIDTH-1:0] CurAddr2 = req_fifo_axi_addr[req_done_ptr];
|
|
wire [1:0] bShift2 = CurAddr2[1:0];
|
|
|
// Read data adaptation
|
// Read data adaptation
|
always_comb begin
|
always_comb begin
|
case (req_fifo_axi_width[req_done_ptr])
|
case (req_fifo_axi_width[req_done_ptr])
|
SCR1_MEM_WIDTH_BYTE : rcvd_rdata = rdata >> (8*bShift2);
|
SCR1_MEM_WIDTH_BYTE : rcvd_rdata = rdata >> (8*bShift2);
|
