| Line 1... |
Line 1... |
-------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------
|
-- Z80_Soc (Z80 System on Chip)
|
-- Z80_Soc (Z80 System on Chip)
|
--
|
--
|
-- Version 0.5 Beta
|
-- Version 0.5 Beta Spartan 3E
|
--
|
--
|
-- Developer: Ronivon Candido Costa
|
-- Developer: Ronivon Candido Costa
|
-- Release Date: 2008 / 04 / 16
|
-- Release Date: 2008 / 04 / 16
|
--
|
--
|
-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
|
-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
|
-- This version developed and tested on: Altera DE1 Development Board
|
-- This version developed and tested on: Diligent Spartan 3E
|
--
|
--
|
-- Peripherals configured (Using Ports):
|
-- Peripherals configured (Using Ports):
|
--
|
--
|
-- 08 KB Internal ROM Read (0x0000h - 0x1FFFh)
|
-- 08 KB Internal ROM Read (0x0000h - 0x1FFFh)
|
-- 08 KB INTERNAL VRAM Write (0x2000h - 0x3FFFh)
|
-- 02 KB INTERNAL VRAM Write (0x2000h - 0x27FFh)
|
-- 48 KB External SRAM Read/Write (0x4000h - 0xFFFFh)
|
-- 16 KB INTERNAL RAM Read/Write (0x4000h - 0xFFFFh)
|
-- 08 Green Leds Out (Port 0x01h)
|
-- 08 Green Leds Out (Port 0x01h)
|
-- 08 Red Leds Out (Port 0x02h)
|
-- 01 LCD display Out (0x3FE0 x 0x3FFF)
|
-- 04 Seven Seg displays Out (Ports 0x10h and 0x11h)
|
-- 04 Switches In (Port 0x20h)
|
-- 36 Pins GPIO0 In/Out (Ports 0xA0h, 0xA1h, 0xA2h, 0xA3h, 0xA4h, 0xC0h)
|
|
-- 36 Pins GPIO1 In/Out (Ports 0xB0h, 0xB1h, 0xB2h, 0xB3h, 0xB4h, 0xC1h)
|
|
-- 08 Switches In (Port 0x20h)
|
|
-- 04 Push buttons In (Port 0x30h)
|
-- 04 Push buttons In (Port 0x30h)
|
-- PS/2 keyboard In (Port 0x80h)
|
-- PS/2 keyboard In (Port 0x80h)
|
-- Video Out (VGA) Out (0x2000h - 0x24B0)
|
-- Video Out (VGA) Out (0x2000h - 0x24B0)
|
--
|
--
|
--
|
--
|
-- Revision history:
|
-- Revision history:
|
--
|
--
|
|
-- 2008/05/11 - Fixed access to RAM and VRAM,
|
|
-- Released same ROM version for DE1 and S3E
|
|
--
|
|
-- 2008/05/01 - Added LCD support for Spartan 3E
|
|
--
|
-- 2008/04(21 - Ported to Spartan 3E
|
-- 2008/04(21 - Ported to Spartan 3E
|
--
|
--
|
-- 2008/04/17 - Added Video support for 80x40 mode
|
-- 2008/04/17 - Added Video support for 80x40 mode
|
-- 2008/04/16 - Release Version 0.5-DE1-Beta
|
-- 2008/04/16 - Release Version 0.5-DE1-Beta
|
--
|
--
|
-- TO-DO:
|
-- TO-DO:
|
|
-- - Implement hardware control for the Rotary knob
|
|
-- - Implement hardware control for the A/D and IO pins
|
-- - Monitor program to introduce Z80 Assmebly codes and run
|
-- - Monitor program to introduce Z80 Assmebly codes and run
|
-- - Serial communication, to download assembly code from PC
|
-- - Serial communication, to download assembly code from PC
|
-- - Add hardware support for 80x40 Video out
|
-- - Add hardware support for 80x40 Video out
|
-- - SD/MMC card interface to read/store data and programs
|
-- - SD/MMC card interface to read/store data and programs
|
-------------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------
|
| Line 78... |
Line 82... |
VGA_VS : out std_logic; -- SYNC
|
VGA_VS : out std_logic; -- SYNC
|
VGA_R, -- Red[3:0]
|
VGA_R, -- Red[3:0]
|
VGA_G, -- Green[3:0]
|
VGA_G, -- Green[3:0]
|
VGA_B : out std_logic; -- Blue[3:0]
|
VGA_B : out std_logic; -- Blue[3:0]
|
SF_D : out std_logic_vector(3 downto 0);
|
SF_D : out std_logic_vector(3 downto 0);
|
LCD_E, LCD_RS, LCD_RW, SF_CE0 : out std_logic
|
LCD_E, LCD_RS, LCD_RW, SF_CE0 : out std_logic;
|
|
AP : out std_logic_vector(15 downto 0);
|
|
DI : out std_logic_vector(7 downto 0);
|
|
DO : out std_logic_vector(7 downto 0);
|
|
WR : out std_logic;
|
|
RD : out std_logic;
|
|
MR : out std_logic;
|
|
IQ : out std_logic
|
);
|
);
|
end Z80SOC_TOP;
|
end Z80SOC_TOP;
|
|
|
architecture rtl of Z80SOC_TOP is
|
architecture rtl of Z80SOC_TOP is
|
|
|
component clk_div
|
component T80se
|
PORT
|
|
(
|
|
clock_25Mhz : IN STD_LOGIC;
|
|
clock_1MHz : OUT STD_LOGIC;
|
|
clock_100KHz : OUT STD_LOGIC;
|
|
clock_10KHz : OUT STD_LOGIC;
|
|
clock_1KHz : OUT STD_LOGIC;
|
|
clock_100Hz : OUT STD_LOGIC;
|
|
clock_10Hz : OUT STD_LOGIC;
|
|
clock_1Hz : OUT STD_LOGIC);
|
|
end component;
|
|
|
|
component T80s
|
|
generic(
|
generic(
|
Mode : integer := 0);
|
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
|
T2Write : integer := 1; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
|
|
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
|
|
);
|
port (
|
port (
|
RESET_n : in std_logic;
|
RESET_n : in std_logic;
|
CLK_n : in std_logic;
|
CLK_n : in std_logic;
|
|
CLKEN : in std_logic;
|
WAIT_n : in std_logic;
|
WAIT_n : in std_logic;
|
INT_n : in std_logic;
|
INT_n : in std_logic;
|
NMI_n : in std_logic;
|
NMI_n : in std_logic;
|
BUSRQ_n : in std_logic;
|
BUSRQ_n : in std_logic;
|
M1_n : out std_logic;
|
M1_n : out std_logic;
|
| Line 117... |
Line 119... |
RFSH_n : out std_logic;
|
RFSH_n : out std_logic;
|
HALT_n : out std_logic;
|
HALT_n : out std_logic;
|
BUSAK_n : out std_logic;
|
BUSAK_n : out std_logic;
|
A : out std_logic_vector(15 downto 0);
|
A : out std_logic_vector(15 downto 0);
|
DI : in std_logic_vector(7 downto 0);
|
DI : in std_logic_vector(7 downto 0);
|
DO : out std_logic_vector(7 downto 0));
|
DO : out std_logic_vector(7 downto 0)
|
|
);
|
|
end component;
|
|
|
|
component sram16k
|
|
port (
|
|
addr : IN std_logic_VECTOR(13 downto 0);
|
|
clk : IN std_logic;
|
|
din : IN std_logic_VECTOR(7 downto 0);
|
|
dout : OUT std_logic_VECTOR(7 downto 0);
|
|
we : IN std_logic);
|
|
end component;
|
|
|
|
component Clock_357Mhz
|
|
PORT (
|
|
clock_50Mhz : IN STD_LOGIC;
|
|
clock_357Mhz : OUT STD_LOGIC);
|
|
end component;
|
|
|
|
component clk_div
|
|
PORT
|
|
(
|
|
clock_25Mhz : IN STD_LOGIC;
|
|
clock_1MHz : OUT STD_LOGIC;
|
|
clock_100KHz : OUT STD_LOGIC;
|
|
clock_10KHz : OUT STD_LOGIC;
|
|
clock_1KHz : OUT STD_LOGIC;
|
|
clock_100Hz : OUT STD_LOGIC;
|
|
clock_10Hz : OUT STD_LOGIC;
|
|
clock_1Hz : OUT STD_LOGIC);
|
end component;
|
end component;
|
|
|
component lcd
|
component lcd
|
port(
|
port(
|
clk, reset : in std_logic;
|
clk, reset : in std_logic;
|
| Line 142... |
Line 173... |
wea: IN std_logic);
|
wea: IN std_logic);
|
end component;
|
end component;
|
|
|
component rom
|
component rom
|
port (
|
port (
|
clk : in std_logic;
|
Clk : in std_logic;
|
addr : in std_logic_vector(12 downto 0);
|
A : in std_logic_vector(11 downto 0);
|
dout : out std_logic_vector(7 downto 0));
|
D : out std_logic_vector(7 downto 0));
|
end component;
|
|
|
|
component Clock_357Mhz
|
|
PORT (
|
|
clock_50Mhz : IN STD_LOGIC;
|
|
clock_357Mhz : OUT STD_LOGIC);
|
|
end component;
|
end component;
|
|
|
component ps2kbd
|
component ps2kbd
|
PORT (
|
PORT (
|
keyboard_clk : inout std_logic;
|
keyboard_clk : inout std_logic;
|
| Line 176... |
Line 201... |
dina: IN std_logic_VECTOR(7 downto 0);
|
dina: IN std_logic_VECTOR(7 downto 0);
|
doutb: OUT std_logic_VECTOR(7 downto 0);
|
doutb: OUT std_logic_VECTOR(7 downto 0);
|
wea: IN std_logic);
|
wea: IN std_logic);
|
end component;
|
end component;
|
|
|
COMPONENT video_80x40
|
COMPONENT video
|
PORT( CLOCK_50 : IN STD_LOGIC;
|
PORT( CLOCK_25 : IN STD_LOGIC;
|
VRAM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
VRAM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
VRAM_ADDR : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
|
VRAM_ADDR : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
|
VRAM_CLOCK : OUT STD_LOGIC;
|
VRAM_CLOCK : OUT STD_LOGIC;
|
VRAM_WREN : OUT STD_LOGIC;
|
VRAM_WREN : OUT STD_LOGIC;
|
VGA_R,
|
VGA_R,
|
| Line 203... |
Line 228... |
signal A : std_logic_vector(15 downto 0);
|
signal A : std_logic_vector(15 downto 0);
|
signal One : std_logic;
|
signal One : std_logic;
|
|
|
signal D_ROM : std_logic_vector(7 downto 0);
|
signal D_ROM : std_logic_vector(7 downto 0);
|
|
|
signal clk25mhz_sig : std_logic;
|
signal clk25mhz : std_logic;
|
signal clk100hz : std_logic;
|
signal clk100hz : std_logic;
|
signal clk10hz : std_logic;
|
signal clk10hz : std_logic;
|
signal clk1hz : std_logic;
|
signal clk1hz : std_logic;
|
|
|
signal vram_addra_sig : std_logic_vector(15 downto 0);
|
signal vram_addra : std_logic_vector(15 downto 0);
|
signal vram_addrb_sig : std_logic_vector(15 downto 0);
|
signal vram_addrb : std_logic_vector(15 downto 0);
|
signal vram_addrb_sigv : std_logic_vector(15 downto 0);
|
signal vram_dina : std_logic_vector(7 downto 0);
|
signal vram_dina_sig : std_logic_vector(7 downto 0);
|
signal vram_dinb : std_logic_vector(7 downto 0);
|
signal vram_dinb_sig : std_logic_vector(7 downto 0);
|
signal vram_douta : std_logic_vector(7 downto 0);
|
signal vram_douta_sig : std_logic_vector(7 downto 0);
|
signal vram_doutb : std_logic_vector(7 downto 0);
|
signal vram_doutb_sig : std_logic_vector(7 downto 0);
|
signal vram_wea : std_logic;
|
signal vram_doutb_sigv : std_logic_vector(7 downto 0);
|
signal vram_web : std_logic;
|
signal vram_wea_sig : std_logic;
|
signal vram_clka : std_logic;
|
signal vram_web_sig : std_logic;
|
signal vram_clkb : std_logic;
|
signal vram_clka_sig : std_logic;
|
|
signal vram_clkb_sig : std_logic;
|
-- sram signals
|
signal vram_clkb_sigv : std_logic;
|
signal sram_addr : std_logic_vector(15 downto 0);
|
|
signal sram_din : std_logic_vector(7 downto 0);
|
|
signal sram_dout : std_logic_vector(7 downto 0);
|
|
signal sram_we : std_logic;
|
|
|
-- LCD signals
|
-- LCD signals
|
signal lcd_wea : std_logic;
|
signal lcd_wea : std_logic;
|
signal lcd_addra : std_logic_vector(4 downto 0);
|
signal lcd_addra : std_logic_vector(4 downto 0);
|
signal lcd_addrb : std_logic_vector(4 downto 0);
|
signal lcd_addrb : std_logic_vector(4 downto 0);
|
| Line 244... |
Line 272... |
|
|
begin
|
begin
|
|
|
Rst_n_s <= not KEY(3);
|
Rst_n_s <= not KEY(3);
|
|
|
writevram: process(Clk_Z80)
|
LEDG <= DO_CPU when (IORQ_n = '0' and Wr_n = '0' and A(7 downto 0) = x"01");
|
begin
|
|
if Clk_Z80'event and Clk_Z80 = '1' then
|
|
if A >= x"2000" and A <= x"27FF" then
|
|
vram_addra_sig <= A - x"2000";
|
|
if Wr_n = '0' and MReq_n = '0' then
|
|
vram_dina_sig <= DO_CPU;
|
|
vram_wea_sig <= '0';
|
|
else
|
|
vram_wea_sig <= '1';
|
|
end if;
|
|
else
|
|
vram_wea_sig <= '1';
|
|
end if;
|
|
end if;
|
|
end process;
|
|
|
|
lcd_process: process(Clk_Z80)
|
-- Write into VRAM
|
begin
|
vram_addra <= A - x"2000" when (A >= x"2000" and A < x"2800");
|
if Clk_Z80'event and Clk_Z80 = '1' then
|
vram_wea <= '0' when (A >= x"2000" and A < x"2800" and Wr_n = '0' and MReq_n = '0') else '1';
|
if A >= x"3FE0" and A < x"4000" then
|
vram_dina <= DO_CPU when (A >= x"2000" and A < x"2800" and Wr_n = '0' and MReq_n = '0');
|
if MReq_n = '0' and Wr_n = '0' then
|
|
lcd_wea <= '0';
|
-- Write into LCD video ram
|
lcd_addra <= A - x"3FE0";
|
lcd_addra <= A - x"3FE0" when (A >= x"3FE0" and A < x"4000" and MReq_n = '0');
|
lcd_dina <= DO_CPU;
|
lcd_wea <= '0' when (A >= x"3FE0" and A < x"4000" and Wr_n = '0' and MReq_n = '0') else '1';
|
else
|
lcd_dina <= DO_CPU when (A >= x"3FE0" and A < x"4000" and Wr_n = '0' and MReq_n = '0');
|
lcd_wea <= '1';
|
|
end if;
|
-- Write into SRAM
|
else
|
sram_addr <= A - x"4000" when (A >= x"4000" and A <= x"7FFF");
|
lcd_wea <= '1';
|
sram_we <= '0' when (A >= x"4000" and A <= x"7FFF" and Wr_n = '0' and MReq_n = '0') else '1';
|
end if;
|
sram_din <= DO_CPU when (A >= x"4000" and A <= x"7FFF" and Wr_n = '0' and MReq_n = '0');
|
end if;
|
|
end process;
|
|
|
|
DI_CPU <= D_ROM when (Rd_n = '0' and MReq_n = '0' and A < x"2000") else
|
DI_CPU <= sram_dout when (Rd_n = '0' and MReq_n = '0' and A >= x"4000") else
|
|
D_ROM when (Rd_n = '0' and MReq_n = '0' and A < x"2000") else
|
("0000" & SW) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"20") else
|
("0000" & SW) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"20") else
|
("0000" & KEY) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"30") else
|
("0000" & KEY) when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"30") else
|
ps2_ascii_reg when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"80");
|
ps2_ascii_reg when (IORQ_n = '0' and Rd_n = '0' and A(7 downto 0) = x"80") else
|
|
"ZZZZZZZZ";
|
-- Process to latch leds and hex displays
|
|
process(Clk_Z80)
|
|
variable LEDG_sig : std_logic_vector(7 downto 0);
|
|
|
|
begin
|
|
|
|
if Clk_Z80'event and Clk_Z80 = '1' then
|
|
if IORQ_n = '0' and Wr_n = '0' then
|
|
-- LEDG
|
|
if A(7 downto 0) = x"01" then
|
|
LEDG_sig := DO_CPU;
|
|
end if;
|
|
end if;
|
|
end if;
|
|
|
|
-- Latches the signals
|
|
LEDG <= LEDG_sig;
|
|
end process;
|
|
|
|
-- the following three processes deals with different clock domain signals
|
-- the following three processes deals with different clock domain signals
|
ps2_process1: process(CLOCK_50)
|
ps2_process1: process(CLOCK_50)
|
begin
|
begin
|
if CLOCK_50'event and CLOCK_50 = '1' then
|
if CLOCK_50'event and CLOCK_50 = '1' then
|
| Line 328... |
Line 322... |
if Clk_Z80'event and Clk_Z80 = '1' then
|
if Clk_Z80'event and Clk_Z80 = '1' then
|
ps2_ascii_reg <= ps2_ascii_reg1;
|
ps2_ascii_reg <= ps2_ascii_reg1;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
|
|
One <= '1';
|
One <= '1';
|
z80_inst: T80s
|
z80_inst: T80se
|
port map (
|
port map (
|
M1_n => open,
|
M1_n => open,
|
MREQ_n => MReq_n,
|
MREQ_n => MReq_n,
|
IORQ_n => IORq_n,
|
IORQ_n => IORq_n,
|
RD_n => Rd_n,
|
RD_n => Rd_n,
|
| Line 346... |
Line 339... |
NMI_n => One,
|
NMI_n => One,
|
RESET_n => Rst_n_s,
|
RESET_n => Rst_n_s,
|
BUSRQ_n => One,
|
BUSRQ_n => One,
|
BUSAK_n => open,
|
BUSAK_n => open,
|
CLK_n => Clk_Z80,
|
CLK_n => Clk_Z80,
|
|
CLKEN => One,
|
A => A,
|
A => A,
|
DI => DI_CPU,
|
DI => DI_CPU,
|
DO => DO_CPU
|
DO => DO_CPU
|
);
|
);
|
|
|
vga80x40_inst: video_80x40 port map (
|
video_out_inst: video port map (
|
CLOCK_50 => CLOCK_50,
|
CLOCK_25 => clk25mhz,
|
VRAM_DATA => vram_doutb_sig,
|
VRAM_DATA => vram_doutb,
|
VRAM_ADDR => vram_addrb_sig(12 downto 0),
|
VRAM_ADDR => vram_addrb(12 downto 0),
|
VRAM_CLOCK => vram_clkb_sig,
|
VRAM_CLOCK => vram_clkb,
|
VRAM_WREN => vram_web_sig,
|
VRAM_WREN => vram_web,
|
VGA_R => VGA_R,
|
VGA_R => VGA_R,
|
VGA_G => VGA_G,
|
VGA_G => VGA_G,
|
VGA_B => VGA_B,
|
VGA_B => VGA_B,
|
VGA_HS => VGA_HS,
|
VGA_HS => VGA_HS,
|
VGA_VS => VGA_VS
|
VGA_VS => VGA_VS
|
);
|
);
|
|
|
vram_inst: vram port map (
|
vram_inst: vram port map (
|
clka => Clk_Z80,
|
clka => Clk_Z80,
|
clkb => vram_clkb_sig,
|
clkb => vram_clkb,
|
wea => vram_wea_sig,
|
wea => vram_wea,
|
addra => vram_addra_sig(10 downto 0),
|
addra => vram_addra(10 downto 0),
|
addrb => vram_addrb_sig(10 downto 0),
|
addrb => vram_addrb(10 downto 0),
|
dina => vram_dina_sig,
|
dina => vram_dina,
|
doutb => vram_doutb_sig
|
doutb => vram_doutb
|
);
|
);
|
|
|
rom_inst: rom
|
rom_inst: rom
|
port map (
|
port map (
|
clk => Clk_Z80,
|
Clk => Clk_Z80,
|
addr => A(12 downto 0),
|
A => A(11 downto 0),
|
dout => D_ROM
|
D => D_ROM
|
);
|
);
|
|
|
ps2_kbd_inst : ps2kbd PORT MAP (
|
ps2_kbd_inst : ps2kbd PORT MAP (
|
keyboard_clk => PS2_CLK,
|
keyboard_clk => PS2_CLK,
|
keyboard_data => PS2_DAT,
|
keyboard_data => PS2_DAT,
|
| Line 392... |
Line 386... |
read => ps2_read,
|
read => ps2_read,
|
scan_ready => ps2_scan_ready,
|
scan_ready => ps2_scan_ready,
|
ps2_ascii_code => ps2_ascii_sig
|
ps2_ascii_code => ps2_ascii_sig
|
);
|
);
|
|
|
|
clk25mhz_proc: process (CLOCK_50)
|
process (CLOCK_50)
|
|
begin
|
begin
|
if CLOCK_50'event and CLOCK_50 = '1' then
|
if CLOCK_50'event and CLOCK_50 = '1' then
|
clk25mhz_sig <= not clk25mhz_sig;
|
clk25mhz <= not clk25mhz;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
clock_z80_inst : Clock_357Mhz
|
|
port map (
|
|
clock_50Mhz => CLOCK_50,
|
|
clock_357Mhz => Clk_Z80
|
|
);
|
|
|
|
clkdiv_inst: clk_div
|
clkdiv_inst: clk_div
|
port map (
|
port map (
|
clock_25Mhz => clk25mhz_sig,
|
clock_25Mhz => clk25mhz,
|
clock_1MHz => open,
|
clock_1MHz => open,
|
clock_100KHz => open,
|
clock_100KHz => open,
|
clock_10KHz => open,
|
clock_10KHz => open,
|
clock_1KHz => open,
|
clock_1KHz => open,
|
clock_100Hz => clk100hz,
|
clock_100Hz => clk100hz,
|
clock_10Hz => clk10hz,
|
clock_10Hz => clk10hz,
|
clock_1Hz => clk1hz
|
clock_1Hz => clk1hz
|
);
|
);
|
|
|
|
clock_z80_inst : Clock_357Mhz
|
|
port map (
|
|
clock_50Mhz => CLOCK_50,
|
|
clock_357Mhz => Clk_Z80
|
|
);
|
|
|
lcd_inst: lcd
|
lcd_inst: lcd
|
port map (
|
port map (
|
clk => CLOCK_50,
|
clk => CLOCK_50,
|
reset => not Rst_n_s,
|
reset => not Rst_n_s,
|
SF_D => SF_D,
|
SF_D => SF_D,
|
| Line 442... |
Line 435... |
dina => lcd_dina,
|
dina => lcd_dina,
|
doutb => lcd_doutb,
|
doutb => lcd_doutb,
|
wea => lcd_wea
|
wea => lcd_wea
|
);
|
);
|
|
|
|
ram16k_inst : sram16k
|
|
port map (
|
|
addr => sram_addr(13 downto 0),
|
|
clk => Clk_Z80,
|
|
din => sram_din,
|
|
dout => sram_dout,
|
|
we => sram_we
|
|
);
|
|
|
end;
|
end;
|
No newline at end of file
|
No newline at end of file
|
