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Line 7... |
-- Release Date: 2008 / 04 / 16
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-- Release Date: 2008 / 04 / 16
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--
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--
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-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
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-- Based on the T80 core: http://www.opencores.org/projects.cgi/web/t80
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-- This version developed and tested on: Altera DE1 Development Board
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-- This version developed and tested on: Altera DE1 Development Board
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--
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--
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-- Please, see the RevisionHistory.txt file for complete features and change history.
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--
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-- Peripherals configured (Using Ports):
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-- Peripherals configured (Using Ports):
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--
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--
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-- 08 KB Internal ROM Read (0x0000h - 0x1FFFh)
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-- 08 KB Internal ROM Read (0x0000h - 0x1FFFh)
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-- 08 KB INTERNAL VRAM Write (0x2000h - 0x3FFFh)
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-- 08 KB INTERNAL VRAM Write (0x2000h - 0x3FFFh)
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-- 48 KB External SRAM Read/Write (0x4000h - 0xFFFFh)
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-- 48 KB External SRAM Read/Write (0x4000h - 0xFFFFh)
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| Line 246... |
Line 248... |
HEX1 <= HEX_DISP1;
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HEX1 <= HEX_DISP1;
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HEX2 <= HEX_DISP2;
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HEX2 <= HEX_DISP2;
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HEX3 <= HEX_DISP3;
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HEX3 <= HEX_DISP3;
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SRAM_ADDR(15 downto 0) <= A - x"4000" when (A >= x"4000" and MReq_n = '0');
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SRAM_ADDR(15 downto 0) <= A - x"4000" when (A >= x"4000" and MReq_n = '0');
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-- SRAM_ADDR(15 downto 0) <= A - x"4000" when (A >= x"4000" and MReq_n = '0') else A;
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-- this is bad --> SRAM_ADDR(15 downto 0) <= A - x"4000";
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SRAM_DQ(15 downto 8) <= (others => 'Z');
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SRAM_DQ(15 downto 8) <= (others => 'Z');
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SRAM_ADDR(17 downto 16) <= "00";
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SRAM_ADDR(17 downto 16) <= "00";
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SRAM_UB_N <= '1';
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SRAM_UB_N <= '1';
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SRAM_LB_N <= '0';
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SRAM_LB_N <= '0';
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SRAM_CE_N <= '0';
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SRAM_CE_N <= '0';
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| Line 260... |
Line 260... |
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-- Write to SRAM (0x4000 - 0xFFFF)
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-- Write to SRAM (0x4000 - 0xFFFF)
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SRAM_DQ(7 downto 0) <= DO_CPU when (Wr_n = '0' and MReq_n = '0' and A >= x"4000") else (others => 'Z');
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SRAM_DQ(7 downto 0) <= DO_CPU when (Wr_n = '0' and MReq_n = '0' and A >= x"4000") else (others => 'Z');
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-- Write into VRAM
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-- Write into VRAM
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-- this is almost ok -->vram_wraddress_sig <= A - x"2000" when (A >= x"2000" and A < x"4000" and MReq_n = '0' and IORQ_n = '1');
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vram_wraddress_sig <= A - x"2000" when (A >= x"2000" and A < x"4000" and MReq_n = '0');
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vram_wraddress_sig <= A - x"2000" when (A >= x"2000" and A < x"4000" and MReq_n = '0');
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-- vram_wraddress_sig <= A - x"2000";
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vram_wren_sig <= not Wr_n when (A >= x"2000" and A < x"4000" and IORQ_n = '1');
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vram_wren_sig <= not Wr_n when (A >= x"2000" and A < x"4000" and IORQ_n = '1');
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vram_data_sig <= DO_CPU when (Wr_n = '0' and MReq_n = '0' and A >= x"2000" and A < x"4000") else (others => 'Z');
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vram_data_sig <= DO_CPU when (Wr_n = '0' and MReq_n = '0' and A >= x"2000" and A < x"4000") else (others => 'Z');
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-- this is ok --> vram_data_sig <= DO_CPU;
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-- Input to Z80
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-- Input to Z80
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DI_CPU <= SRAM_DQ(7 downto 0) when (Rd_n = '0' and MReq_n = '0' and A >= x"4000") else
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DI_CPU <= SRAM_DQ(7 downto 0) when (Rd_n = '0' and MReq_n = '0' and A >= x"4000") else
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-- vram_q_sig when (A >= x"2000" and A < x"4000") else
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-- vram_q_sig when (A >= x"2000" and A < x"4000") else
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D_ROM when (Rd_n = '0' and MReq_n = '0' and A < x"2000") else
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D_ROM when (Rd_n = '0' and MReq_n = '0' and A < x"2000") else
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