URL
https://opencores.org/ocsvn/zap/zap/trunk
[/] [zap/] [trunk/] [README.md] - Diff between revs 26 and 32
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 26 |
Rev 32 |
Line 25... |
Line 25... |
|
|
Wishbone B3 compatible 32-bit bus.
|
Wishbone B3 compatible 32-bit bus.
|
|
|
### Documentation
|
### Documentation
|
|
|
Please see the HTML file at *doc/html/zap\_doc.htm*
|
Please see the PDF file at *doc/ZAP_PROCESSOR_CORE_DATASHEET.pdf*
|
|
|
### Features
|
### Features
|
|
|
- Fully synthesizable Verilog-2001 core.
|
- Fully synthesizable Verilog-2001 core.
|
- Store buffer for improved performance.
|
- Store buffer for improved performance.
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.