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### Introduction
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### Introduction
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The ZAP processor is a 10 stage pipelined processor for FPGA with support for cache and MMU (ARMv5T compliant).
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The ZAP processor is a 10 stage pipelined processor for FPGA with support for cache and MMU (ARMv5T compliant).
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Please note that the processor is *not* an ARM clone but a completely different RTL design, written from scratch (in FPGA compliant Verilog-2001), that can run ARM v5T binaries, hence, no particular ARMX number is specified.
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Please note that the processor is *not* an ARM clone but a completely different RTL design, written from scratch (in FPGA compliant Verilog-2001), that can run ARM v5T binaries (both user and kernel code), hence, no particular ARMX number is specified.
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This project was created for the ORCONF-2016 Student Design Contest.
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This project was originally created for the ORCONF-2016 Student Design Contest.
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ZAP is specifically designed to work with FPGAs.
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ZAP is specifically designed to work with FPGAs. To keep the code generic across FPGA vendors, inference based coding style is followed.
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#### Repos
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#### Repos
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This project is hosted on Github and Opencores.
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GIT: https://github.com/krevanth/ZAP
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GIT: https://github.com/krevanth/ZAP
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SVN: https://opencores.org/projects/zap
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SVN: https://opencores.org/projects/zap
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#### Features
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#### Features
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|L1 Data TLB | Direct mapped |
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|L1 Data TLB | Direct mapped |
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|Bus Interface | 32-bit Wishbone B3 Linear incrementing burst |
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|Bus Interface | 32-bit Wishbone B3 Linear incrementing burst |
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|Cache/TLB Lock Support | No |
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|Cache/TLB Lock Support | No |
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|CP15 Compliance | v5T (No fine pages) |
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|CP15 Compliance | v5T (No fine pages) |
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|FCSE Support | Yes |
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|FCSE Support | Yes |
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|Cache Read Speed (Hit) | 320MB/s @ 80MHz CLK |
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|Cache Write Speed(Hit) | 160MB/s @ 80MHz CLK |
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|Cache Line Size | 16B |
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* 10-stage pipeline design. Pipeline has extensive bypass network to resolve dependencies. Most operations execute at a rate of 1 operation per clock.
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* 10-stage pipeline design. Pipeline has extensive bypass network to resolve dependencies. Most operations execute at a rate of 1 operation per clock.
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* 2 write ports for the register file to allow LDR/STR with writeback to execute as a single instruction.
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* 2 write ports for the register file to allow LDR/STR with writeback to execute as a single instruction.
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* Instructions of ALU + Shift can allow execution of subsequent commands with dependencies if the subsequent command doesn't use the shifter. This is done by having a dual feedback network.
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* Instructions of ALU + Shift can allow execution of subsequent commands with dependencies if the subsequent command doesn't use the shifter. This is done by having a dual feedback network.
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* The core is specifically designed for use in FGPA and relies on FGPA inference to allow portability across FPGA vendors.
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* The core is specifically designed for use in FGPA and relies on FGPA inference to allow portability across FPGA vendors.
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| input | [31:0] | i_wb_dat | Wishbone B3 signal. |
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| input | [31:0] | i_wb_dat | Wishbone B3 signal. |
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| output | | o_wb_stb_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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| output | | o_wb_stb_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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| output | | o_wb_cyc_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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| output | | o_wb_cyc_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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| output | [31:0] | o_wb_adr_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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| output | [31:0] | o_wb_adr_nxt | IGNORE THIS PORT. LEAVE OPEN. |
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### Directory Structure
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├── LICENSE
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├── makefile
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├── README.md
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└── src
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├── rtl
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│ └── cpu
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│ ├── zap_alu_main.v
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│ ├── zap_cache_fsm.v
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│ ├── zap_cache_tag_ram.v
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│ ├── zap_cache.v
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│ ├── zap_core.v
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│ ├── zap_cp15_cb.v
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│ ├── zap_decode_main.v
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│ ├── zap_decode.v
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│ ├── zap_decompile.v
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│ ├── zap_defines.vh
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│ ├── zap_fetch_main.v
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│ ├── zap_fifo.v
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│ ├── zap_functions.vh
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│ ├── zap_issue_main.v
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│ ├── zap_localparams.vh
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│ ├── zap_mem_inv_block.v
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│ ├── zap_memory_main.v
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│ ├── zap_predecode_compress.v
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│ ├── zap_predecode_coproc.v
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│ ├── zap_predecode_main.v
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│ ├── zap_predecode_mem_fsm.v
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│ ├── zap_ram_simple.v
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│ ├── zap_register_file.v
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│ ├── zap_shifter_main.v
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│ ├── zap_shifter_multiply.v
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│ ├── zap_shift_shifter.v
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│ ├── zap_sync_fifo.v
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│ ├── zap_thumb_decoder.v
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│ ├── zap_tlb_check.v
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│ ├── zap_tlb_fsm.v
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│ ├── zap_tlb.v
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│ ├── zap_top.v
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│ ├── zap_wb_adapter.v
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│ ├── zap_wb_merger.v
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│ └── zap_writeback.v
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├── scripts
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│ ├── bin2vlog.pl
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│ ├── Config.cfg_template
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│ ├── makefile
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│ ├── run_sim.pl
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│ └── uart_input.bash
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├── testbench
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│ ├── chip_top.v
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│ ├── External_IP
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│ │ └── uart16550
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│ │ ├── doc
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│ │ │ ├── CHANGES.txt
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│ │ │ ├── src
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│ │ │ │ └── UART_spec.doc
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│ │ │ └── UART_spec.pdf
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│ │ └── rtl
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│ │ ├── raminfr.v
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│ │ ├── uart_debug_if.v
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│ │ ├── uart_defines.v
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│ │ ├── uart_receiver.v
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│ │ ├── uart_regs.v
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│ │ ├── uart_rfifo.v
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│ │ ├── uart_sync_flops.v
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│ │ ├── uart_tfifo.v
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│ │ ├── uart_top.v
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│ │ ├── uart_transmitter.v
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│ │ └── uart_wb.v
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│ ├── ram.v
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│ ├── timer.v
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│ ├── uart_rx_logger.v
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│ ├── uart_tx_dumper.v
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│ ├── vic.v
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│ └── zap_tb.v
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└── ts
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├── arm_test
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│ ├── arm_test.c
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│ ├── arm_test.ld
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│ ├── arm_test.s
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│ ├── Config.cfg
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│ ├── Description.txt
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│ └── makefile
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├── factorial
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│ ├── Config.cfg
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│ ├── Description.txt
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│ ├── factorial.c
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│ ├── factorial.ld
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│ ├── factorial.s
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│ └── makefile
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├── makefile
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├── thumb_test
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│ ├── Config.cfg
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│ ├── Description.txt
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│ ├── linker.ld
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│ ├── main.c
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│ ├── makefile
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│ └── thumb.s
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└── uart
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├── Config.cfg
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├── Description.txt
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├── irq_handler.c
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├── main.c
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├── makefile
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├── uart.c
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├── uart.h
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├── uart.ld
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└── uart.s
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### Run Sample Tests
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### Run Sample Tests
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*Tested on Ubuntu 16.04 LTS/18.04 LTS*
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*Tested on Ubuntu 16.04 LTS/18.04 LTS*
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Let the variable $test_name hold the name of the test. See the src/ts directory for some basic tests pre-installed. Available test names are: factorial, arm_test, thumb_test, uart. New tests can be added using these as starting templates. Please note that these will be run on the SOC platform (chip_top) that consist of the ZAP processor, 2 x UARTs, a VIC and a timer.
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Let the variable $test_name hold the name of the test. See the src/ts directory for some basic tests pre-installed. Available test names are: factorial, arm_test, thumb_test, uart. New tests can be added using these as starting templates. Please note that these will be run on the SOC platform (chip_top) that consist of the ZAP processor, 2 x UARTs, a VIC and a timer.
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```bash
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```bash
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sudo apt-get install sudo apt-get install gcc-arm-none-eabi binutils-arm-none-eabi gdb openocd iverilog gtkwave make perl xterm
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sudo apt-get install gcc-arm-none-eabi binutils-arm-none-eabi gdb openocd
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sudo apt-get install iverilog gtkwave make perl xterm
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cd $PROJ_ROOT/src/ts/$test_name # $PROJ_ROOT is the project directory.
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cd $PROJ_ROOT/src/ts/$test_name # $PROJ_ROOT is the project directory.
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make # Runs the test using IVerilog.
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make # Runs the test using IVerilog.
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cd $PROJ_ROOT/obj/ts/$test_name # Switch to object folder.
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cd $PROJ_ROOT/obj/ts/$test_name # Switch to object folder.
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gvim zap.log.gz # View the log file
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gvim zap.log.gz # View the log file
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gtkwave zap.vcd.gz # Exists if selected by Config.cfg. See PDF document for more information.
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gtkwave zap.vcd.gz # Exists if selected by Config.cfg of that test case.
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```
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```
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To use this processor in your SOC, instantiate this top level CPU module in your project: /src/rtl/cpu/zap_top.v
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To use this processor in your SOC, instantiate this top level CPU module in your project: /src/rtl/cpu/zap_top.v
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### FPGA Timing Performance (Vivado, Retime Enabled)
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### FPGA Timing Performance (Vivado, Retime Enabled)
|
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