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/*
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* Copyright (c) 2008 Zeus Gomez Marmolejo <zeus@opencores.org>
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*
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* This file is part of the Zet processor. This processor is free
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* hardware; you can redistribute it and/or modify it under the terms of
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* the GNU General Public License as published by the Free Software
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* Foundation; either version 3, or (at your option) any later version.
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*
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* Zet is distrubuted in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Zet; see the file COPYING. If not, see
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* <http://www.gnu.org/licenses/>.
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*/
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`timescale 1ns/10ps
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`include "defines.v"
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module cpu (
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`ifdef DEBUG
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output [15:0] cs,
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output [15:0] ip,
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output [ 2:0] state,
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output [ 2:0] next_state,
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output [ 5:0] iralu,
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output [15:0] x,
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output [15:0] y,
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output [15:0] imm,
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output [15:0] aluo,
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output [15:0] ax,
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output [15:0] dx,
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output [15:0] bp,
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output [15:0] si,
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output [15:0] es,
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input dbg_block,
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output [15:0] c,
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output [ 3:0] addr_c,
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output [15:0] cpu_dat_o,
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output [15:0] d,
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output [ 3:0] addr_d,
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output byte_exec,
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output [ 8:0] flags,
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output end_seq,
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output ext_int,
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output cpu_block,
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`endif
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// Wishbone master interface
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input wb_clk_i,
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input wb_rst_i,
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input [15:0] wb_dat_i,
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output [15:0] wb_dat_o,
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output [19:1] wb_adr_o,
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output wb_we_o,
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output wb_tga_o, // io/mem
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output [ 1:0] wb_sel_o,
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output wb_stb_o,
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output wb_cyc_o,
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input wb_ack_i,
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input wb_tgc_i, // intr
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output wb_tgc_o // inta
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);
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// Net declarations
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`ifndef DEBUG
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wire [15:0] cs, ip;
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wire [15:0] imm;
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wire [15:0] cpu_dat_o;
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wire byte_exec;
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wire cpu_block;
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`endif
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wire [`IR_SIZE-1:0] ir;
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wire [15:0] off;
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wire [19:0] addr_exec, addr_fetch;
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wire byte_fetch, fetch_or_exec;
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wire of, zf, cx_zero;
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wire div_exc;
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wire wr_ip0;
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wire ifl;
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wire cpu_byte_o;
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wire cpu_m_io;
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wire [19:0] cpu_adr_o;
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wire wb_block;
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wire [15:0] cpu_dat_i;
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wire cpu_we_o;
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wire [15:0] iid_dat_i;
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// Module instantiations
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fetch fetch0 (
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`ifdef DEBUG
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.state (state),
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.next_state (next_state),
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.ext_int (ext_int),
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.end_seq (end_seq),
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`endif
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.clk (wb_clk_i),
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.rst (wb_rst_i),
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.cs (cs),
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.ip (ip),
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.of (of),
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.zf (zf),
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.data (cpu_dat_i),
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.ir (ir),
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.off (off),
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.imm (imm),
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.pc (addr_fetch),
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.cx_zero (cx_zero),
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.bytefetch (byte_fetch),
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.fetch_or_exec (fetch_or_exec),
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.block (cpu_block),
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.div_exc (div_exc),
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.wr_ip0 (wr_ip0),
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.intr (wb_tgc_i),
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.ifl (ifl),
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.inta (wb_tgc_o)
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);
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exec exec0 (
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`ifdef DEBUG
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.x (x),
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.y (y),
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.aluo (aluo),
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.ax (ax),
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.dx (dx),
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.bp (bp),
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.si (si),
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.es (es),
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.c (c),
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.addr_c (addr_c),
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.omemalu (d),
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.addr_d (addr_d),
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.flags (flags),
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`endif
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.ir (ir),
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.off (off),
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.imm (imm),
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.cs (cs),
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.ip (ip),
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.of (of),
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.zf (zf),
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.cx_zero (cx_zero),
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.clk (wb_clk_i),
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.rst (wb_rst_i),
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.memout (iid_dat_i),
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.wr_data (cpu_dat_o),
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.addr (addr_exec),
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.we (cpu_we_o),
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.m_io (cpu_m_io),
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.byteop (byte_exec),
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.block (cpu_block),
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.div_exc (div_exc),
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.wrip0 (wr_ip0),
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.ifl (ifl)
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);
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wb_master wm0 (
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.cpu_byte_o (cpu_byte_o),
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.cpu_memop (ir[`MEM_OP]),
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.cpu_m_io (cpu_m_io),
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.cpu_adr_o (cpu_adr_o),
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.cpu_block (wb_block),
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.cpu_dat_i (cpu_dat_i),
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.cpu_dat_o (cpu_dat_o),
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.cpu_we_o (cpu_we_o),
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.wb_clk_i (wb_clk_i),
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.wb_rst_i (wb_rst_i),
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.wb_dat_i (wb_dat_i),
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.wb_dat_o (wb_dat_o),
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.wb_adr_o (wb_adr_o),
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.wb_we_o (wb_we_o),
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.wb_tga_o (wb_tga_o),
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.wb_sel_o (wb_sel_o),
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.wb_stb_o (wb_stb_o),
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.wb_cyc_o (wb_cyc_o),
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.wb_ack_i (wb_ack_i)
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);
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// Assignments
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assign cpu_adr_o = fetch_or_exec ? addr_exec : addr_fetch;
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assign cpu_byte_o = fetch_or_exec ? byte_exec : byte_fetch;
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assign iid_dat_i = wb_tgc_o ? wb_dat_i : cpu_dat_i;
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`ifdef DEBUG
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assign iralu = ir[28:23];
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assign cpu_block = wb_block | dbg_block;
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`else
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assign cpu_block = wb_block;
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`endif
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endmodule
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module wb_master (
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input cpu_byte_o,
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input cpu_memop,
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input cpu_m_io,
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input [19:0] cpu_adr_o,
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output reg cpu_block,
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output reg [15:0] cpu_dat_i,
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input [15:0] cpu_dat_o,
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input cpu_we_o,
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input wb_clk_i,
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input wb_rst_i,
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input [15:0] wb_dat_i,
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output [15:0] wb_dat_o,
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output reg [19:1] wb_adr_o,
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output wb_we_o,
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output wb_tga_o,
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output reg [ 1:0] wb_sel_o,
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output reg wb_stb_o,
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output reg wb_cyc_o,
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input wb_ack_i
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);
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// Register and nets declarations
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reg [ 1:0] cs; // current state
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reg [ 1:0] ns; // next state
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wire op; // in an operation
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wire odd_word; // unaligned word
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wire a0; // address 0 pin
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wire [15:0] blw; // low byte (sign extended)
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wire [15:0] bhw; // high byte (sign extended)
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wire [19:1] adr1; // next address (for unaligned acc)
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wire [ 1:0] sel_o; // bus byte select
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// Declare the symbolic names for states
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localparam [1:0]
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IDLE = 2'd0,
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stb1_lo = 2'd1,
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stb2_hi = 2'd2;
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// Assignments
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assign op = (cpu_memop | cpu_m_io);
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assign odd_word = (cpu_adr_o[0] & !cpu_byte_o);
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assign a0 = cpu_adr_o[0];
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assign blw = { {8{wb_dat_i[7]}}, wb_dat_i[7:0] };
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assign bhw = { {8{wb_dat_i[15]}}, wb_dat_i[15:8] };
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assign adr1 = a0 ? (cpu_adr_o[19:1] + 1'b1)
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: cpu_adr_o[19:1];
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assign wb_dat_o = a0 ? { cpu_dat_o[7:0], cpu_dat_o[15:8] }
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: cpu_dat_o;
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assign wb_we_o = cpu_we_o;
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assign wb_tga_o = cpu_m_io;
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assign sel_o = a0 ? 2'b10 : (cpu_byte_o ? 2'b01 : 2'b11);
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// Behaviour
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// cpu_dat_i
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always @(posedge wb_clk_i)
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cpu_dat_i <= (cs == IDLE) ?
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(wb_ack_i ?
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(a0 ? bhw : (cpu_byte_o ? blw : wb_dat_i))
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: cpu_dat_i)
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: ((cs == stb1_lo && wb_ack_i) ?
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{ wb_dat_i[7:0], cpu_dat_i[7:0] }
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: cpu_dat_i);
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// outputs setup
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always @(*)
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case (cs)
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default:
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begin
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cpu_block <= op;
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wb_adr_o <= cpu_adr_o[19:1];
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wb_sel_o <= sel_o;
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wb_stb_o <= op;
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wb_cyc_o <= op;
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end
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stb1_lo:
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begin
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cpu_block <= 1'b1;
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wb_adr_o <= adr1;
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wb_sel_o <= 2'b01;
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wb_stb_o <= 1'b1;
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wb_cyc_o <= 1'b1;
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end
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stb2_hi:
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begin
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cpu_block <= wb_ack_i;
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wb_adr_o <= adr1;
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wb_sel_o <= 2'b01;
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wb_stb_o <= 1'b0;
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wb_cyc_o <= 1'b0;
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end
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endcase
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// state machine
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// cs - current state
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always @(posedge wb_clk_i)
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cs <= wb_rst_i ? IDLE : ns;
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// ns - next state
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always @(*)
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case (cs)
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default: ns <= wb_ack_i ?
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(op ? (odd_word ? stb1_lo : stb2_hi) : IDLE)
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: IDLE;
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stb1_lo: ns <= wb_ack_i ? stb2_hi : stb1_lo;
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stb2_hi: ns <= wb_ack_i ? stb2_hi : IDLE;
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endcase
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endmodule
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