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[/] [zet86/] [trunk/] [sim/] [memory.v] - Diff between revs 27 and 35
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| Rev 27 |
Rev 35 |
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`timescale 1ns/10ps
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`timescale 1ns/10ps
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module memory (
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module memory (
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input clk,
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// Wishbone slave interface
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input [19:0] addr,
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input wb_clk_i,
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input [15:0] wr_data,
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input wb_rst_i,
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output [15:0] rd_data,
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input [15:0] wb_dat_i,
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input we,
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output [15:0] wb_dat_o,
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input byte_m
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input [19:1] wb_adr_i,
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input wb_we_i,
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input [ 1:0] wb_sel_i,
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input wb_stb_i,
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input wb_cyc_i,
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output wb_ack_o
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);
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);
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// Registers and nets
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// Registers and nets
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wire [19:0] addr1;
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reg [15:0] ram[2**19-1:0];
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reg [7:0] ram[2**20-1:0];
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wire we;
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wire [7:0] bhw, blw;
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// Assignments
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// Assignments
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assign rd_data = byte_m ? { {8{ram[addr][7]}}, ram[addr]}
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assign wb_dat_o = ram[wb_adr_i];
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: {ram[addr1], ram[addr]};
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assign wb_ack_o = wb_stb_i;
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assign addr1 = addr + 20'd1;
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assign we = wb_we_i & wb_stb_i & wb_cyc_i;
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assign bhw = wb_sel_i[1] ? wb_dat_i[15:8]
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: ram[wb_adr_i][15:8];
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assign blw = wb_sel_i[0] ? wb_dat_i[7:0]
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: ram[wb_adr_i][7:0];
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// Behaviour
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// Behaviour
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always @(posedge clk)
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always @(posedge wb_clk_i)
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if (we) if (byte_m) ram[addr] <= wr_data[7:0];
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if (we) ram[wb_adr_i] <= { bhw, blw };
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else { ram[addr1], ram[addr] } <= wr_data;
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initial $readmemh("/home/zeus/zet/sim/data.rtlrom", ram, 20'hf0000);
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initial $readmemh("/home/zeus/zet/sim/data.rtlrom",
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ram, 19'h78000);
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endmodule
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endmodule
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