URL https://opencores.org/ocsvn/zet86/zet86/trunk

Subversion Repositories zet86

[/] [zet86/] [trunk/] [sim/] [modelsim/] [tb.do] - Diff between revs 14 and 21

Rev 14	Rev 21
Line 1...	Line 1...
`#vdel -all -lib work`	`vdel -all -lib work`
`vlib work`	`vlib work`
`vlog -work work +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v`	`vlog -work work -lint +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v`
`vlog -work work +incdir+.. ../memory.v ../testbench.v`	`vlog -work work +incdir+.. ../memory.v ../testbench.v`
`vsim -novopt -t ns work.testbench`	`vsim -novopt -t ns work.testbench`
`add wave /testbench/clk`	`add wave /testbench/clk`
`add wave /testbench/rst`	`add wave /testbench/rst`
`add wave -radix hexadecimal /testbench/cpu0/fetch0/pc`	`add wave -radix hexadecimal /testbench/cpu0/fetch0/pc`