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https://opencores.org/ocsvn/zet86/zet86/trunk
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| Rev 27 |
Rev 28 |
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#vdel -all -lib work
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vdel -all -lib work
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#vlib work
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vlib work
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#vlog -work work -lint +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v ../../rtl-model/rotate.v
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vlog -work work -lint +incdir+../../rtl-model ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v ../../rtl-model/rotate.v
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#vlog -work work +incdir+.. ../memory.v ../testbench.v
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vlog -work work +incdir+.. ../memory.v ../testbench.v
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vsim -novopt -t ns work.testbench
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vsim -novopt -t ns work.testbench
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add wave -label clk /testbench/clk
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add wave -label clk /testbench/clk
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add wave -label rst /testbench/rst
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add wave -label rst /testbench/rst
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add wave -label pc -radix hexadecimal /testbench/cpu0/fetch0/pc
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add wave -label pc -radix hexadecimal /testbench/cpu0/fetch0/pc
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add wave -divider fetch
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add wave -divider fetch
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add wave -label addr_d /testbench/cpu0/exec0/reg0/addr_d
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add wave -label addr_d /testbench/cpu0/exec0/reg0/addr_d
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add wave -label wr /testbench/cpu0/exec0/reg0/wr
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add wave -label wr /testbench/cpu0/exec0/reg0/wr
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add wave -label we /testbench/we
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add wave -label we /testbench/we
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add wave -label ack_i /testbench/ack_i
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add wave -label ack_i /testbench/ack_i
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add wave -label fetch_or_exec /testbench/cpu0/fetch_or_exec
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add wave -label fetch_or_exec /testbench/cpu0/fetch_or_exec
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run 50us
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No newline at end of file
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#run 50us
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