| Line 1... |
Line 1... |
vdel -all -lib work
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#vdel -all -lib work
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vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims
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vmap unisims /opt/Xilinx/10.1/modelsim/verilog/unisims
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vlib work
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vlib work
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vlog -work work -lint +incdir+../../rtl-model +incdir+.. ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v ../../rtl-model/util/div_su.v ../../rtl-model/util/div_uu.v ../../rtl-model/rotate.v
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vlog -work work -lint +incdir+../../rtl-model +incdir+.. ../../rtl-model/regfile.v ../../rtl-model/alu.v ../../rtl-model/cpu.v ../../rtl-model/exec.v ../../rtl-model/fetch.v ../../rtl-model/jmp_cond.v ../../rtl-model/util/primitives.v ../../rtl-model/util/div_su.v ../../rtl-model/util/div_uu.v ../../rtl-model/rotate.v
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vlog -work work +incdir+.. ../memory.v ../testbench.v ../mult.v
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vlog -work work +incdir+.. ../memory.v ../testbench.v ../mult.v
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vlog -work unisims /opt/Xilinx/10.1/ISE/verilog/src/glbl.v
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vlog -work unisims /opt/Xilinx/10.1/ISE/verilog/src/glbl.v
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| Line 19... |
Line 19... |
add wave -label need_off /testbench/cpu0/fetch0/need_off
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add wave -label need_off /testbench/cpu0/fetch0/need_off
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add wave -label need_imm /testbench/cpu0/fetch0/need_imm
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add wave -label need_imm /testbench/cpu0/fetch0/need_imm
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add wave -label ir /testbench/cpu0/fetch0/ir
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add wave -label ir /testbench/cpu0/fetch0/ir
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add wave -label imm -radix hexadecimal /testbench/cpu0/fetch0/imm
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add wave -label imm -radix hexadecimal /testbench/cpu0/fetch0/imm
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add wave -label off -radix hexadecimal /testbench/cpu0/fetch0/off
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add wave -label off -radix hexadecimal /testbench/cpu0/fetch0/off
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add wave -label intr -radix hexadecimal /testbench/intr
|
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add wave -label intr -radix hexadecimal /testbench/cpu0/fetch0/decode0/intr
|
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add wave -label inta -radix hexadecimal /testbench/inta
|
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add wave -label ext_int -radix hexadecimal /testbench/cpu0/fetch0/decode0/ext_int
|
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add wave -label repz_pr -radix hexadecimal /testbench/cpu0/fetch0/repz_pr
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add wave -divider mem
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add wave -divider mem
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add wave -label cs -radix hexadecimal /testbench/cpu0/wm0/cs
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add wave -label cs -radix hexadecimal /testbench/cpu0/wm0/cs
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add wave -label op -radix hexadecimal /testbench/cpu0/wm0/op
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add wave -label op -radix hexadecimal /testbench/cpu0/wm0/op
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add wave -label block /testbench/cpu0/wm0/cpu_block
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add wave -label block /testbench/cpu0/wm0/cpu_block
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add wave -label dat_o -radix hexadecimal sim:/testbench/dat_o
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add wave -label dat_o -radix hexadecimal sim:/testbench/dat_o
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| Line 33... |
Line 38... |
add wave -label stb_o -radix hexadecimal /cpu0/wm0/wb_stb_o
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add wave -label stb_o -radix hexadecimal /cpu0/wm0/wb_stb_o
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add wave -label cyc_o -radix hexadecimal /cpu0/wm0/wb_cyc_o
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add wave -label cyc_o -radix hexadecimal /cpu0/wm0/wb_cyc_o
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add wave -label ack_i -radix hexadecimal /cpu0/wm0/wb_ack_i
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add wave -label ack_i -radix hexadecimal /cpu0/wm0/wb_ack_i
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add wave -label we_o -radix hexadecimal /cpu0/wm0/wb_we_o
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add wave -label we_o -radix hexadecimal /cpu0/wm0/wb_we_o
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add wave -label tga_o -radix hexadecimal /cpu0/wm0/wb_tga_o
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add wave -label tga_o -radix hexadecimal /cpu0/wm0/wb_tga_o
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add wave -label cpu_dat_i -radix hexadecimal /cpu0/wm0/cpu_dat_i
|
|
add wave -divider alu
|
add wave -divider alu
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add wave -label x -radix hexadecimal /testbench/cpu0/exec0/a
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add wave -label x -radix hexadecimal /testbench/cpu0/exec0/a
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add wave -label y -radix hexadecimal /testbench/cpu0/exec0/bus_b
|
add wave -label y -radix hexadecimal /testbench/cpu0/exec0/bus_b
|
add wave -label t -radix hexadecimal /testbench/cpu0/exec0/alu0/t
|
add wave -label t -radix hexadecimal /testbench/cpu0/exec0/alu0/t
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add wave -label func -radix hexadecimal /testbench/cpu0/exec0/alu0/func
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add wave -label func -radix hexadecimal /testbench/cpu0/exec0/alu0/func
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| Line 47... |
Line 51... |
add wave -label addr_d /testbench/cpu0/exec0/reg0/addr_d
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add wave -label addr_d /testbench/cpu0/exec0/reg0/addr_d
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add wave -label wr /testbench/cpu0/exec0/reg0/wr
|
add wave -label wr /testbench/cpu0/exec0/reg0/wr
|
add wave -label we /testbench/we
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add wave -label we /testbench/we
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add wave -label ack /testbench/ack
|
add wave -label ack /testbench/ack
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add wave -label fetch_or_exec /testbench/cpu0/fetch_or_exec
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add wave -label fetch_or_exec /testbench/cpu0/fetch_or_exec
|
run 15us
|
add wave -divider regfile
|
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add wave -label cx -radix hexadecimal /testbench/cpu0/exec0/reg0/r\[1\]
|
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add wave -label tmp -radix hexadecimal /testbench/cpu0/exec0/reg0/r\[13\]
|
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add wave -label cs -radix hexadecimal /testbench/cpu0/exec0/reg0/r\[9\]
|
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add wave -label ip -radix hexadecimal /testbench/cpu0/exec0/reg0/r\[15\]
|
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add wave -divider Wishbone-Master
|
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add wave -label cpu_dat_i -radix hexadecimal /cpu0/wm0/cpu_dat_i
|
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add wave -label cs -radix hexadecimal /cpu0/wm0/cs
|
|
|
|
run 20us
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