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[/] [zet86/] [trunk/] [sim/] [testbench.v] - Diff between revs 14 and 21

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Rev 14 Rev 21
Line 8... Line 8...
  wire [19:0] addr;
  wire [19:0] addr;
  wire        we;
  wire        we;
  wire        m_io;
  wire        m_io;
  wire        byte_m;
  wire        byte_m;
  wire        ack_i;
  wire        ack_i;
 
  wire        stb;
 
 
  reg         clk, rst;
  reg         clk, rst;
  reg [15:0]  io_reg;
  reg [15:0]  io_reg;
  reg [ 1:0]  ack;
  reg [ 1:0]  ack;
 
 
  // Module instantiations
  // Module instantiations
  memory mem0 (clk, addr, wr_data, mem_data, we & ~m_io, byte_m);
  memory mem0 (clk, addr, wr_data, mem_data, stb & we & ~m_io, byte_m);
 
 
  cpu cpu0 (
  cpu cpu0 (
    .clk_i  (clk),
    .clk_i  (clk),
    .rst_i  (rst),
    .rst_i  (rst),
    .dat_i  (rd_data),
    .dat_i  (rd_data),
    .dat_o  (wr_data),
    .dat_o  (wr_data),
    .adr_o  (addr),
    .adr_o  (addr),
    .we_o   (we),
    .we_o   (we),
    .mio_o  (m_io),
    .mio_o  (m_io),
    .byte_o (byte_m),
    .byte_o (byte_m),
 
    .stb_o  (stb),
    .ack_i  (ack_i)
    .ack_i  (ack_i)
  );
  );
 
 
  // Assignments
  // Assignments
  assign io_data = (addr[15:0]==16'hb7) ? io_reg : 16'd0;
  assign io_data = (addr[15:0]==16'hb7) ? io_reg : 16'd0;

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