Subversion Repositories zet86

  wire        tga;

  wire        tga;

  wire [ 1:0] sel;

  wire [ 1:0] sel;

  wire        stb;

  wire        stb;

  wire        cyc;

  wire        cyc;

  wire        ack, mem_ack, io_ack;

  wire        ack, mem_ack, io_ack;

  reg         clk;

  reg         clk;

  reg         rst;

  reg         rst;

  reg  [15:0] io_reg;

  reg  [15:0] io_reg;

  // Module instantiations

  // Module instantiations

  memory mem0 (

  memory mem0 (

    .wb_clk_i (clk),

    .wb_clk_i (clk),

    .wb_rst_i (rst),

    .wb_rst_i (rst),

    .wb_dat_i (dat_o),

    .wb_dat_i (dat_o),

    .wb_we_o  (we),

    .wb_we_o  (we),

    .wb_tga_o (tga),

    .wb_tga_o (tga),

    .wb_sel_o (sel),

    .wb_sel_o (sel),

    .wb_stb_o (stb),

    .wb_stb_o (stb),

    .wb_cyc_o (cyc),

    .wb_cyc_o (cyc),

  );

  );

  // Assignments

  // Assignments

  assign io_dat_i = (adr[15:1]==15'h5b) ? { io_reg[7:0], 8'h0 }

  assign io_dat_i = (adr[15:1]==15'h5b) ? { io_reg[7:0], 8'h0 }

    : ((adr[15:1]==15'h5c) ? { 8'h0, io_reg[15:8] } : 16'h0);

    : ((adr[15:1]==15'h5c) ? { 8'h0, io_reg[15:8] } : 16'h0);

  assign ack    = tga ? io_ack : mem_ack;

  assign ack    = tga ? io_ack : mem_ack;

  assign io_ack = stb;

  assign io_ack = stb;

  // Behaviour

  // Behaviour

  always #1 clk = ~clk;

  always #1 clk = ~clk;

  initial

  initial

    begin

    begin

         clk <= 1'b1;

         clk <= 1'b1;

         rst <= 1'b0;

         rst <= 1'b0;

      #5 rst <= 1'b1;

      #5 rst <= 1'b1;

      #2 rst <= 1'b0;

      #2 rst <= 1'b0;

    end

    end

endmodule

endmodule

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