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[/] [zet86/] [trunk/] [soc/] [timer.v] - Diff between revs 49 and 52
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module timer (
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/*
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* Phase accumulator clock:
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* Fo = Fc * N / 2^bits
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* here N: 12507 and bits: 32
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* it gives a frequency of 18.200080376 Hz
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*/
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module timer #(
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parameter res = 33, // bit resolution (default: 33 bits)
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parameter phase = 12507 // phase value for the counter
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)
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(
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// Wishbone slave interface
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// Wishbone slave interface
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input wb_clk_i,
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input wb_clk_i,
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input wb_rst_i,
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input wb_rst_i,
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output reg wb_tgc_o, // intr
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output reg wb_tgc_o // intr
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input wb_tgc_i // inta
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);
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);
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// Registers and nets
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// Registers and nets
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reg [17:0] cnt;
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reg [res-1:0] cnt;
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reg old_clk2;
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reg old_clk2;
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reg pulse;
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wire clk2;
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wire clk2;
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// Continuous assignments
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// Continuous assignments
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assign clk2 = cnt[17];
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assign clk2 = cnt[res-1];
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// Behaviour
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// Behaviour
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// cnt
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// cnt
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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cnt <= wb_rst_i ? 18'h00 : (cnt + 18'h1);
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cnt <= wb_rst_i ? 0 : (cnt + phase);
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// old_clk2
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// old_clk2
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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old_clk2 <= wb_rst_i ? 1'b0 : clk2;
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old_clk2 <= wb_rst_i ? 1'b0 : clk2;
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// pulse
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always @(posedge wb_clk_i)
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pulse <= wb_rst_i ? 1'b0 : (clk2!=old_clk2);
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// intr
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// intr
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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wb_tgc_o <= wb_rst_i ? 1'b0
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wb_tgc_o <= wb_rst_i ? 1'b0 : (!old_clk2 & clk2);
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: ((pulse & !wb_tgc_i) ? 1'b1
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: (wb_tgc_o ? !wb_tgc_i : 1'b0));
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endmodule
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endmodule
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