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/*
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* Copyright (c) 2008 Zeus Gomez Marmolejo <zeus@opencores.org>
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*
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* This file is part of the Zet processor. This processor is free
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* hardware; you can redistribute it and/or modify it under the terms of
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* the GNU General Public License as published by the Free Software
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* Foundation; either version 3, or (at your option) any later version.
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*
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* Zet is distrubuted in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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* License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with Zet; see the file COPYING. If not, see
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* <http://www.gnu.org/licenses/>.
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*/
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`timescale 1ns/10ps
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`timescale 1ns/10ps
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module ram_2k (clk, rst, cs, we, addr, rdata, wdata);
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module ram_2k (clk, rst, cs, we, addr, rdata, wdata);
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// IO Ports
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// IO Ports
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input clk;
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input clk;
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.SSR (rst),
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.SSR (rst),
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.WE (we));
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.WE (we));
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defparam ram.INIT_00 = 256'h554456_2043504F53_20302E3176_20726F737365636F7270_2074655A;
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defparam ram.INIT_00 = 256'h554456_2043504F53_20302E3176_20726F737365636F7270_2074655A;
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/*
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/*
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defparam ram.INIT_00 = 256'h3130393837363534333231303938373635343332313039383736353433323130;
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defparam ram.INIT_00 = 256'h31303938373635343332313039383736_35343332313039383736353433323130;
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defparam ram.INIT_01 = 256'h3332313039383736353433323130393837363534333231303938373635343332;
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defparam ram.INIT_01 = 256'h33323130393837363534333231303938_37363534333231303938373635343332;
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defparam ram.INIT_02 = 256'h3534333231303938373635343332313039383736353433323130393837363534;
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defparam ram.INIT_02 = 256'h3139383736353433323130393837363534;
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defparam ram.INIT_03 = 256'h3736353433323130393837363534333231303938373635343332313039383736;
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defparam ram.INIT_03 = 256'h43000000;
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defparam ram.INIT_04 = 256'h3938373635343332313039383736353433323130393837363534333231303938;
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defparam ram.INIT_05 = 256'h32;
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defparam ram.INIT_05 = 256'h3130393837363534333231303938373635343332313039383736353433323130;
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defparam ram.INIT_07 = 256'h3300000000000000000000000000000000;
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defparam ram.INIT_06 = 256'h3332313039383736353433323130393837363534333231303938373635343332;
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defparam ram.INIT_0A = 256'h34;
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defparam ram.INIT_07 = 256'h3534333231303938373635343332313039383736353433323130393837363534;
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defparam ram.INIT_0C = 256'h3500000000000000000000000000000000;
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defparam ram.INIT_08 = 256'h3736353433323130393837363534333231303938373635343332313039383736;
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defparam ram.INIT_0F = 256'h36;
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defparam ram.INIT_09 = 256'h3938373635343332313039383736353433323130393837363534333231303938;
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defparam ram.INIT_11 = 256'h3700000000000000000000000000000000;
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defparam ram.INIT_14 = 256'h38;
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defparam ram.INIT_16 = 256'h3900000000000000000000000000000000;
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defparam ram.INIT_19 = 256'h30;
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defparam ram.INIT_1B = 256'h3100000000000000000000000000000000;
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defparam ram.INIT_1E = 256'h32;
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defparam ram.INIT_20 = 256'h3300000000000000000000000000000000;
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defparam ram.INIT_23 = 256'h34;
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defparam ram.INIT_25 = 256'h3500000000000000000000000000000000;
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defparam ram.INIT_28 = 256'h36;
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defparam ram.INIT_2A = 256'h3700000000000000000000000000000000;
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defparam ram.INIT_2D = 256'h38;
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defparam ram.INIT_2F = 256'h3900000000000000000000000000000000;
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defparam ram.INIT_32 = 256'h30;
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defparam ram.INIT_34 = 256'h3100000000000000000000000000000000;
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defparam ram.INIT_37 = 256'h32;
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defparam ram.INIT_39 = 256'h3300000000000000000000000000000000;
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defparam ram.INIT_3C = 256'h31303938373635343332313039383736_35343332313039383736353433323134;
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defparam ram.INIT_3D = 256'h33323130393837363534333231303938_37363534333231303938373635343332;
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defparam ram.INIT_3E = 256'h35343332313039383736353433323130_39383736353433323130393837363534;
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defparam ram.INIT_3F = 256'h37363534333231303938373635343332_31303938373635343332313039383736;
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*/
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*/
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endmodule
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endmodule
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