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https://opencores.org/ocsvn/zet86/zet86/trunk
[/] [zet86/] [trunk/] [soc/] [vga/] [rtl/] [vdu.v] - Diff between revs 40 and 41
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| Rev 40 |
Rev 41 |
| Line 118... |
Line 118... |
wire [15:0] out_data;
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wire [15:0] out_data;
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wire fg_or_bg;
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wire fg_or_bg;
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wire stb;
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wire stb;
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wire brown_bg;
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wire brown_bg;
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wire brown_fg;
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wire brown_fg;
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wire status_reg1;
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wire vh_retrace;
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wire v_retrace;
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// Module instantiation
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// Module instantiation
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char_rom vdu_char_rom (
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char_rom vdu_char_rom (
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.clk (wb_clk_i),
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.clk (wb_clk_i),
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.rst (wb_rst_i),
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.rst (wb_rst_i),
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| Line 169... |
Line 172... |
assign brown_fg = (vga_fg_colour==3'd6) && !intense;
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assign brown_fg = (vga_fg_colour==3'd6) && !intense;
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assign brown_bg = (vga_bg_colour==3'd6);
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assign brown_bg = (vga_bg_colour==3'd6);
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assign wr_pos = wb_tga_i & wb_stb_i & wb_cyc_i & wb_we_i;
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assign wr_pos = wb_tga_i & wb_stb_i & wb_cyc_i & wb_we_i;
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assign v_retrace = !video_on_v;
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assign vh_retrace = v_retrace | !video_on_h;
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assign status_reg1 = { 11'b0, v_retrace, 3'b0, vh_retrace };
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// Behaviour
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// Behaviour
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// CPU write interface
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// CPU write interface
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if (wb_rst_i)
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if (wb_rst_i)
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| Line 203... |
Line 210... |
begin
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begin
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wb_dat_o <= 16'h0;
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wb_dat_o <= 16'h0;
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wb_ack_o <= 16'h0;
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wb_ack_o <= 16'h0;
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end
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end
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else
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else
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if (wb_tga_i)
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begin
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wb_dat_o <= status_reg1;
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wb_ack_o <= stb;
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end
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else
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begin
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begin
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wb_dat_o <= vga4_rw ? out_data : wb_dat_o;
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wb_dat_o <= vga4_rw ? out_data : wb_dat_o;
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wb_ack_o <= vga4_rw ? 1'b1 : (wb_ack_o && stb);
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wb_ack_o <= vga4_rw ? 1'b1 : (wb_ack_o && stb);
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end
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end
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