| Line 28... |
Line 28... |
input wb_we_i,
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input wb_we_i,
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input wb_tga_i,
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input wb_tga_i,
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input [ 1:0] wb_sel_i,
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input [ 1:0] wb_sel_i,
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input wb_stb_i,
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input wb_stb_i,
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input wb_cyc_i,
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input wb_cyc_i,
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output reg wb_ack_o,
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output wb_ack_o,
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// VGA pad signals
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// VGA pad signals
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output reg [ 1:0] vga_red_o,
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output reg [ 1:0] vga_red_o,
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output reg [ 1:0] vga_green_o,
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output reg [ 1:0] vga_green_o,
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output reg [ 1:0] vga_blue_o,
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output reg [ 1:0] vga_blue_o,
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| Line 104... |
Line 104... |
reg [6:0] col1_addr; // 0 to 79
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reg [6:0] col1_addr; // 0 to 79
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reg [4:0] row1_addr; // 0 to 49 (25 * 2 - 1)
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reg [4:0] row1_addr; // 0 to 49 (25 * 2 - 1)
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reg [6:0] hor_addr; // 0 to 79
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reg [6:0] hor_addr; // 0 to 79
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reg [6:0] ver_addr; // 0 to 124
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reg [6:0] ver_addr; // 0 to 124
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reg vga0_we;
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reg vga0_we;
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reg vga0_rw, vga1_rw, vga2_rw, vga3_rw, vga4_rw;
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reg vga0_rw, vga1_rw, vga2_rw, vga3_rw, vga4_rw, vga5_rw;
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reg vga1_we;
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reg vga1_we;
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reg vga2_we;
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reg vga2_we;
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reg buff_we;
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reg buff_we;
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reg [7:0] buff_data_in;
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reg [7:0] buff_data_in;
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reg attr_we;
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reg attr_we;
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| Line 191... |
Line 191... |
assign wr_cur_end = wr_reg & (reg_adr==4'hb);
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assign wr_cur_end = wr_reg & (reg_adr==4'hb);
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assign v_retrace = !video_on_v;
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assign v_retrace = !video_on_v;
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assign vh_retrace = v_retrace | !video_on_h;
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assign vh_retrace = v_retrace | !video_on_h;
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assign status_reg1 = { 11'b0, v_retrace, 3'b0, vh_retrace };
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assign status_reg1 = { 11'b0, v_retrace, 3'b0, vh_retrace };
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assign wb_ack_o = wb_tga_i ? stb : vga5_rw;
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// Behaviour
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// Behaviour
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// CPU write interface
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// CPU write interface
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if (wb_rst_i)
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if (wb_rst_i)
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begin
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begin
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attr0_addr <= 11'b0;
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attr0_addr <= 11'b0;
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| Line 219... |
Line 219... |
buff_data_in <= wb_dat_i[7:0];
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buff_data_in <= wb_dat_i[7:0];
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end
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end
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end
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end
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// CPU read interface
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// CPU read interface
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// wb_dat_o
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if (wb_rst_i)
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wb_dat_o <= wb_rst_i ? 16'h0 : (wb_tga_i ? status_reg1
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begin
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: (vga4_rw ? out_data : wb_dat_o));
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wb_dat_o <= 16'h0;
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wb_ack_o <= 16'h0;
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end
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else
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if (wb_tga_i)
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begin
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wb_dat_o <= status_reg1;
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wb_ack_o <= stb;
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end
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else
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begin
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wb_dat_o <= vga4_rw ? out_data : wb_dat_o;
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wb_ack_o <= vga4_rw ? 1'b1 : (wb_ack_o && stb);
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end
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// Control registers
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// Control registers
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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reg_adr <= wb_rst_i ? 4'h0
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reg_adr <= wb_rst_i ? 4'h0
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: (wr_adr ? wb_dat_i[3:0] : reg_adr);
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: (wr_adr ? wb_dat_i[3:0] : reg_adr);
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| Line 311... |
Line 298... |
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vga2_we <= 1'b0;
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vga2_we <= 1'b0;
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vga2_rw <= 1'b0;
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vga2_rw <= 1'b0;
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vga3_rw <= 1'b0;
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vga3_rw <= 1'b0;
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vga4_rw <= 1'b0;
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vga4_rw <= 1'b0;
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vga5_rw <= 1'b0;
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ver_addr <= 7'b0;
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ver_addr <= 7'b0;
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hor_addr <= 7'b0;
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hor_addr <= 7'b0;
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buff_addr <= 10'b0;
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buff_addr <= 10'b0;
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attr_addr <= 10'b0;
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attr_addr <= 10'b0;
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| Line 361... |
Line 349... |
attr_addr <= vga2_rw ? attr0_addr : vga_addr;
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attr_addr <= vga2_rw ? attr0_addr : vga_addr;
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buff_we <= vga2_rw ? (buff0_we & vga2_we) : 1'b0;
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buff_we <= vga2_rw ? (buff0_we & vga2_we) : 1'b0;
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attr_we <= vga2_rw ? (attr0_we & vga2_we) : 1'b0;
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attr_we <= vga2_rw ? (attr0_we & vga2_we) : 1'b0;
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vga3_rw <= vga2_rw;
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vga3_rw <= vga2_rw;
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vga4_rw <= vga3_rw;
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vga4_rw <= vga3_rw;
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vga5_rw <= vga4_rw;
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end
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end
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// Video shift register
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// Video shift register
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always @(posedge wb_clk_i)
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always @(posedge wb_clk_i)
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if (wb_rst_i)
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if (wb_rst_i)
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