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Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [asm/] [testdiv.S] - Diff between revs 50 and 69

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Rev 50	Rev 69
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`; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`	`; Project: Zip CPU -- a small, lightweight, RISC CPU soft core`
`;`	`;`
`; Purpose: Tests the libraries signed division algorithm.`	`; Purpose: Tests the libraries signed division algorithm.`
`;`	`;`
`; Creator: Dan Gisselquist, Ph.D.`	`; Creator: Dan Gisselquist, Ph.D.`
`; Gisselquist Tecnology, LLC`	`; Gisselquist Technology, LLC`
`;`	`;`
`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`	`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
`;`	`;`
`; Copyright (C) 2015, Gisselquist Technology, LLC`	`; Copyright (C) 2015, Gisselquist Technology, LLC`
`;`	`;`
Line 31...	Line 31...
`;`	`;`
`; Registers:`	`; Registers:`
`; R12 Peripheral base`	`; R12 Peripheral base`
`; R11 Address of our one memory variable`	`; R11 Address of our one memory variable`
`;`	`;`
	`/* something else */`
`#include "sys.i"`	`#include "sys.i"`
`start:`	`start:`
`LDI 0xc0000000,R12 ; Get the address of our peripheral base`	`LDI 0xc0000000,R12 ; Get the address of our peripheral base`
`MOV $1(PC),R11 ; Get a memory address for a variable`	`MOV $1(PC),R11 ; Get a memory address for a variable`
`BRA skip_test_variable`	`BRA skip_test_variable`
`test_variable:`	`test_variable:`
`.DAT 0`	`WORD 0`
`skip_test_variable:`	`skip_test_variable:`
`LDI $-1,R0 ; Start the watchdog timer`	`LDI $-1,R0 ; Start the watchdog timer`
`STO R0,sys.bus.wdt(R12)`	`STO R0,sys.bus.wdt(R12)`
`LSR $1,R0 ; R0 now = 0x7fffffff`	`LSR $1,R0 ; R0 now = 0x7fffffff`
`STO R0,sys.bus.tma(R12)`	`STO R0,sys.bus.tma(R12)`
Line 83...	Line 84...
`TST -1,R11`	`TST -1,R11`
`HALT.Z`	`HALT.Z`
`BUSY`	`BUSY`

`test_div_program:`	`test_div_program:`
`SUB 1,SP`
`;`	`;`
`LDI 1,R11`	`LDI 1,R11`
`LDI 5,R0`	`LDI 5,R0`
`LDI 1,R1`	`LDI 1,R1`
`LDI 5,R2`	`LDI 5,R2`
`LDI 0,R3`	`LDI 0,R3`
`MOV __HERE__+3(PC),R4`	`MOV __HERE__+2(PC),R4`
`STO R4,1(SP)`
`BRA test_divs`	`BRA test_divs`

`;`	`;`
`LDI 2,R11`	`LDI 2,R11`
`LDI 5,R0`	`LDI 5,R0`
`LDI 2,R1`	`LDI 2,R1`
`LDI 2,R2`	`LDI 2,R2`
`LDI 1,R3`	`LDI 1,R3`
`MOV __HERE__+3(PC),R4`	`MOV __HERE__+2(PC),R4`
`STO R4,1(SP)`
`BRA test_divs`	`BRA test_divs`

`;`	`;`
`LDI 3,R11`	`LDI 3,R11`
`LDI 0xb53d0,R0`	`LDI 0xb53d0,R0`
`LDI 0x2d,R1`	`LDI 0x2d,R1`
`LDI 16496,R2`	`LDI 16496,R2`
`LDI 32,R3`	`LDI 32,R3`
`MOV __HERE__+3(PC),R4`	`MOV __HERE__+2(PC),R4`
`STO R4,1(SP)`
`BRA test_divs`	`BRA test_divs`

`;`	`;`
`LDI 4,R11`	`LDI 4,R11`
`LDI 2031890191,R0`	`LDI 2031890191,R0`
`LDI 120193795,R1`	`LDI 120193795,R1`
`LDI 16,R2`	`LDI 16,R2`
`LDI 108789471,R3`	`LDI 108789471,R3`
`MOV __HERE__+3(PC),R4`	`MOV __HERE__+2(PC),R4`
`STO R4,1(SP)`
`BRA test_divs`	`BRA test_divs`

`;`	`;`
`LDI 5,R11`	`LDI 5,R11`
`LDI 203553,R0`	`LDI 203553,R0`
`LDI 142580994,R1`	`LDI 142580994,R1`
`LDI 0,R2`	`LDI 0,R2`
`LDI 203553,R3`	`LDI 203553,R3`
`MOV __HERE__+3(PC),R4`	`MOV __HERE__+2(PC),R4`
`STO R4,1(SP)`
`BRA test_divs`	`BRA test_divs`

`;`	`;`
`LDI 6,R11`	`LDI 6,R11`
`LDI 142580994,R0`	`LDI 142580994,R0`
`LDI 203553,R1`	`LDI 203553,R1`
`LDI 700,R2`	`LDI 700,R2`
`LDI 93894,R3`	`LDI 93894,R3`
`MOV __HERE__+3(PC),R4`	`MOV __HERE__+2(PC),R4`
`STO R4,1(SP)`
`BRA test_divs`	`BRA test_divs`

`;`	`;`
`LDI 7,R11`	`LDI 7,R11`
`LDI 142580994,R0`	`LDI 142580994,R0`
`LDI 2499,R1`	`LDI 2499,R1`
`LDI 57055,R2`	`LDI 57055,R2`
`LDI 549,R3`	`LDI 549,R3`
`MOV __HERE__+3(PC),R4`	`MOV __HERE__+2(PC),R4`
`STO R4,1(SP)`
`BRA test_divs`	`BRA test_divs`

`;`	`;`
`LDI 8,R11`	`LDI 8,R11`
`LDI -142580994,R0`	`LDI -142580994,R0`
`LDI 2499,R1`	`LDI 2499,R1`
`LDI -57055,R2`	`LDI -57055,R2`
`LDI -549,R3`	`LDI -549,R3`
`MOV __HERE__+3(PC),R4`	`MOV __HERE__+2(PC),R4`
`STO R4,1(SP)`
`BRA test_divs`	`BRA test_divs`

`;`	`;`
`LDI 9,R11`	`LDI 9,R11`
`LDI 142580994,R0`	`LDI 142580994,R0`
`LDI -2499,R1`	`LDI -2499,R1`
`LDI -57055,R2`	`LDI -57055,R2`
`LDI 549,R3`	`LDI 549,R3`
`MOV __HERE__+3(PC),R4`	`MOV __HERE__+2(PC),R4`
`STO R4,1(SP)`
`BRA test_divs`	`BRA test_divs`

`;`	`;`
`LDI 10,R11`	`LDI 10,R11`
`LDI -142580994,R0`	`LDI -142580994,R0`
`LDI -2499,R1`	`LDI -2499,R1`
`LDI 57055,R2`	`LDI 57055,R2`
`LDI -549,R3`	`LDI -549,R3`
`MOV __HERE__+3(PC),R4`	`MOV __HERE__+2(PC),R4`
`STO R4,1(SP)`
`BRA test_divs`	`BRA test_divs`

`;`	`;`
`CLR R11`	`CLR R11`
`TRAP 0`	`TRAP 0`
Line 193...	Line 183...
`test_divs:`	`test_divs:`
`; R0 = Numerator`	`; R0 = Numerator`
`; R1 = Denominator`	`; R1 = Denominator`
`; R2 = Integer result`	`; R2 = Integer result`
`; R3 = Remainder`	`; R3 = Remainder`
	`; R4 = Return address`
`; R11= Test failure ID`	`; R11= Test failure ID`
`SUB 1,SP`	`MOV R2,R5`
`MOV R2,R4`	`MOV R3,R6`
`MOV R3,R5`	`MOV __HERE__+2(PC),R2`
`MOV __HERE__+3(PC),R2`	`BRA lib_divs`
`STO R2,1(SP)`	`CMP R0,R5`
`BRA divs`
`CMP R0,R4`
`BNZ test_failure`	`BNZ test_failure`
`CMP R1,R5`	`CMP R1,R6`
`BNZ test_failure`	`BNZ test_failure`
`ADD 1,SP`	`JMP R4`
`RETN`

`test_failure:`	`test_failure:`
`TRAP 0`	`TRAP 0`
`NOOP`	`NOOP`
`BUSY`	`BUSY`

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[/] [zipcpu/] [trunk/] [bench/] [asm/] [testdiv.S] - Diff between revs 50 and 69