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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Filename: testdiv.S
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;
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; Project: Zip CPU -- a small, lightweight, RISC CPU soft core
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;
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; Purpose: Tests the libraries signed division algorithm.
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;
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; Creator: Dan Gisselquist, Ph.D.
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; Gisselquist Tecnology, LLC
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Copyright (C) 2015, Gisselquist Technology, LLC
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;
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; This program is free software (firmware): you can redistribute it and/or
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; modify it under the terms of the GNU General Public License as published
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; by the Free Software Foundation, either version 3 of the License, or (at
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; your option) any later version.
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;
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; This program is distributed in the hope that it will be useful, but WITHOUT
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; ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
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; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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; for more details.
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;
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; License: GPL, v3, as defined and found on www.gnu.org,
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; http://www.gnu.org/licenses/gpl.html
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;
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; Registers:
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; R12 Peripheral base
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; R11 Address of our one memory variable
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;
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#include "sys.i"
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start:
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LDI 0xc0000000,R12 ; Get the address of our peripheral base
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MOV $1(PC),R11 ; Get a memory address for a variable
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BRA skip_test_variable
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test_variable:
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.DAT 0
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skip_test_variable:
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LDI $-1,R0 ; Start the watchdog timer
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STO R0,sys.bus.wdt(R12)
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LSR $1,R0 ; R0 now = 0x7fffffff
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STO R0,sys.bus.tma(R12)
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LSR $1,R0 ; R0 now = 0x3fffffff
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STO R0,sys.bus.tmb(R12)
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LSR $1,R0
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STO R0,sys.bus.tmc(R12)
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;
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CLR R0
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wdt_test_loop:
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ADD $1,R0
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LOD (R11),R1
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CMP R0,R1
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STO.LT R0,(R11)
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TST -1,R0
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BLT wdt_test_program_is_broken
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BRA wdt_test_loop
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wdt_test_program_is_broken:
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HALT
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entry:
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entry:
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; Set up a test program
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; Set up a test program
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MOV test_div_program(PC),uPC
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MOV test_div_program(PC),uPC
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MOV top_of_stack(PC),uSP
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MOV top_of_stack(PC),uSP
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; Run it in user space
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; Run it in user space
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