URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [bench/] [asm/] [wdt.S] - Diff between revs 11 and 40

Rev 11	Rev 40
Line 33...	Line 33...
`;`	`;`
`; Registers:`	`; Registers:`
`; R12 Peripheral base`	`; R12 Peripheral base`
`; R11 Address of our one memory variable`	`; R11 Address of our one memory variable`
`;`	`;`
	`#include "sys.i"`
`start:`	`start:`
`CLR R12 ; Get the address of our peripheral base`	`LDI 0xc0000000,R12 ; Get the address of our peripheral base`
`LDIHI $c000h,R12`	`MOV $1(PC),R11 ; Get a memory address for a variable`
`MOV $1+PC,R11 ; Get a memory address for a variable`	`BRA skip_test_variable`
`BRA $1`	`test_variable:`
`.DAT 0`	`.DAT 0`
	`skip_test_variable:`
`LDI $-1,R0 ; Start the watchdog timer`	`LDI $-1,R0 ; Start the watchdog timer`
`STO R0,$1(R12)`	`STO R0,sys.bus.wdt(R12)`
	`LSR $1,R0 ; R0 now = 0x7fffffff`
	`STO R0,sys.bus.tma(R12)`
	`LSR $1,R0 ; R0 now = 0x3fffffff`
	`STO R0,sys.bus.tmb(R12)`
`LSR $1,R0`	`LSR $1,R0`
`STO R0,$4(R12)`	`STO R0,sys.bus.tmc(R12)`
`LSR $1,R0`
`STO R0,$5(R12)`
`LSR $1,R0`
`STO R0,$6(R12)`
`;`	`;`
`CLR R0`	`CLR R0`
`loop:`	`wdt_test_loop:`
`ADD $1,R0`	`ADD $1,R0`
`LOD (R11),R1`	`LOD (R11),R1`
`CMP R0,R1`	`CMP R0,R1`
`STO.LT R0,(R11)`	`STO.LT R0,(R11)`
`TST R0`	`TST -1,R0`
`BLT $2`	`BLT wdt_test_program_is_broken`
`BRA $-7`	`BRA wdt_test_loop`

	`wdt_test_program_is_broken:`
`HALT`	`HALT`