| Line 48... |
Line 48... |
// DMIPS: 38.0 100 MHz (sim) 0.38 // 20151211 (new ISA)
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// DMIPS: 38.0 100 MHz (sim) 0.38 // 20151211 (new ISA)
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// DMIPS: 40.5 100 MHz (sim) 0.41 // 20151212 (H/W DIV)
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// DMIPS: 40.5 100 MHz (sim) 0.41 // 20151212 (H/W DIV)
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// DMIPS: 8.2 100 MHz (sim) 0.08 // 20151104--!pipelined
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// DMIPS: 8.2 100 MHz (sim) 0.08 // 20151104--!pipelined
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// DMIPS: 60.1 100 MHz (sim) 0.60 // 20151215 (New PF)
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// DMIPS: 60.1 100 MHz (sim) 0.60 // 20151215 (New PF)
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// DMIPS: 60.0 100 MHz (sim) 0.60 // 20151226 (BugFix)
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// DMIPS: 60.0 100 MHz (sim) 0.60 // 20151226 (BugFix)
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// DMIPS: 100 MHz (sim) 0.67 // 20160406 (??)
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// DMIPS: 100 MHz (sim) 0.58 // 20160409 (BugFix)
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// On real hardware:
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// On real hardware:
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// DMIPS: 24.7 100 MHz (basys) 0.25 // Initial baseline
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// DMIPS: 24.7 100 MHz (basys) 0.25 // Initial baseline
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// DMIPS: 30.6 100 MHz (basys) 0.31 // 20151017
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// DMIPS: 30.6 100 MHz (basys) 0.31 // 20151017
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// DMIPS: 48.4 100 MHz (basys) 0.48 // 20151227 (New pf/ISA)
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// DMIPS: 48.4 100 MHz (basys) 0.48 // 20151227 (New pf/ISA)
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//
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//
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| Line 837... |
Line 839... |
ADD R2,R5
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ADD R2,R5
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STO R3,(R5)
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STO R3,(R5)
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STO R3,1(R5)
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STO R3,1(R5)
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STO R2,30(R5)
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STO R2,30(R5)
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MOV R2,R5
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MOV R2,R5
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MPYU 50,R5 ; R5 = 50 * R2 = 50 * loc
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MPY 50,R5 ; R5 = 50 * R2 = 50 * loc
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ADD R1,R5 ; R5 = &b[loc][0]
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ADD R1,R5 ; R5 = &b[loc][0]
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MOV R5,R6 ; R6 = &b[loc][0]
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MOV R5,R6 ; R6 = &b[loc][0]
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ADD R2,R5 ; R5 = &b[loc][loc]
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ADD R2,R5 ; R5 = &b[loc][loc]
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MOV R2,R4 ; R4 = loc = index
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MOV R2,R4 ; R4 = loc = index
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proc_8_top_of_loop:
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proc_8_top_of_loop:
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| Line 1380... |
Line 1382... |
CMP R6,R5
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CMP R6,R5
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BGE dhrystone_end_while_loop
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BGE dhrystone_end_while_loop
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dhrystone_while_loop:
|
dhrystone_while_loop:
|
// lcl_int_3 = 5 * lcl_int_1 - lcl_int_2;
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// lcl_int_3 = 5 * lcl_int_1 - lcl_int_2;
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MOV R5,R7
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MOV R5,R7
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LDI 5,R0
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MPY 5,R7
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MPYS R0,R7
|
|
SUB R6,R7
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SUB R6,R7
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STO R7,lcl_int_3(SP)
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STO R7,lcl_int_3(SP)
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#ifndef SKIP_SHORT_CIRCUITS
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#ifndef SKIP_SHORT_CIRCUITS
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CMP 7,R7
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CMP 7,R7
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BUSY.NZ
|
BUSY.NZ
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| Line 1503... |
Line 1504... |
BUSY.NZ
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BUSY.NZ
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#endif
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#endif
|
//
|
//
|
// lcl_int_2 = lcl_int_2 * lcl_int_1;
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// lcl_int_2 = lcl_int_2 * lcl_int_1;
|
LOD lcl_int_1(SP),R5
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LOD lcl_int_1(SP),R5
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MPYS R5,R6 ; lcl_int_2 =
|
MPY R5,R6 ; lcl_int_2 =
|
// lcl_int_1 = lcl_int_2 / lcl_int_3;
|
// lcl_int_1 = lcl_int_2 / lcl_int_3;
|
#ifdef HARDWARE_DIVIDE
|
#ifdef HARDWARE_DIVIDE
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LOD lcl_int_3(SP),R1
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LOD lcl_int_3(SP),R1
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MOV R6,R0
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MOV R6,R0
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DIVS R1,R0
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DIVS R1,R0
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| Line 1523... |
Line 1524... |
#endif
|
#endif
|
STO R0,lcl_int_1(SP) ;;; TODO FAILS HERE (Watched it fail!)
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STO R0,lcl_int_1(SP) ;;; TODO FAILS HERE (Watched it fail!)
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// lcl_int_2 = 7 * ( lcl_int_2 - lcl_int_3) - lcl_int_1;
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// lcl_int_2 = 7 * ( lcl_int_2 - lcl_int_3) - lcl_int_1;
|
LOD lcl_int_3(SP),R2
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LOD lcl_int_3(SP),R2
|
SUB R2,R6
|
SUB R2,R6
|
MPYS 7,R6
|
MPY 7,R6
|
SUB R0,R6
|
SUB R0,R6
|
// proc_2(&lcl_int_1);
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// proc_2(&lcl_int_1);
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#ifndef SKIP_SHORT_CIRCUITS
|
#ifndef SKIP_SHORT_CIRCUITS
|
LOD lcl_int_1(SP),R0
|
LOD lcl_int_1(SP),R0
|
CMP 1,R0
|
CMP 1,R0
|
