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[/] [zipcpu/] [trunk/] [bench/] [asm/] [zipdhry.S] - Diff between revs 69 and 74

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Rev 69	Rev 74
Line 47...	Line 47...
`// DMIPS: 37.5 100 MHz (sim) 0.38 // 20151017`	`// DMIPS: 37.5 100 MHz (sim) 0.38 // 20151017`
`// DMIPS: 38.0 100 MHz (sim) 0.38 // 20151211 (new ISA)`	`// DMIPS: 38.0 100 MHz (sim) 0.38 // 20151211 (new ISA)`
`// DMIPS: 40.5 100 MHz (sim) 0.41 // 20151212 (H/W DIV)`	`// DMIPS: 40.5 100 MHz (sim) 0.41 // 20151212 (H/W DIV)`
`// DMIPS: 8.2 100 MHz (sim) 0.08 // 20151104--!pipelined`	`// DMIPS: 8.2 100 MHz (sim) 0.08 // 20151104--!pipelined`
`// DMIPS: 60.1 100 MHz (sim) 0.60 // 20151215 (New PF)`	`// DMIPS: 60.1 100 MHz (sim) 0.60 // 20151215 (New PF)`
`// DMIPS: 54.8 100 MHz (sim) 0.55 // 20151219`	`// DMIPS: 60.0 100 MHz (sim) 0.60 // 20151226 (BugFix)`
`// On real hardware:`	`// On real hardware:`
`// DMIPS: 24.7 100 MHz (basys) 0.25 // Initial baseline`	`// DMIPS: 24.7 100 MHz (basys) 0.25 // Initial baseline`
`// DMIPS: 30.6 100 MHz (basys) 0.31 // 20151017`	`// DMIPS: 30.6 100 MHz (basys) 0.31 // 20151017`
	`// DMIPS: 48.4 100 MHz (basys) 0.48 // 20151227 (New pf/ISA)`
`//`	`//`
`// (And, under Verilator, if the cache holds the entire 4kW program: 55.1 DMIPS)`	`// (And, under Verilator, if the cache holds the entire 4kW program: 55.1 DMIPS)`
`//`	`//`
`//`	`//`
`// with no loop unrolling nor function inlining`	`// with no loop unrolling nor function inlining`
Line 155...	Line 156...
`//`	`//`
`#define PIPELINED_STRCPY`	`#define PIPELINED_STRCPY`
`#define PIPELINED_STRCMP`	`#define PIPELINED_STRCMP`
`//`	`//`
`//`	`//`
	`dev.scope.cpu equ 0x0120`
`sys.ctr.mtask equ 0xc0000008`	`sys.ctr.mtask equ 0xc0000008`
`// int main(int argc, char **argv) {`	`// int main(int argc, char **argv) {`
`// dhrystone();`	`// dhrystone();`
`// }`	`// }`
	`// #define LOAD_ADDRESS entry+PC`
	`#define LOAD_ADDRESS lcl_strcpy+PC`
`entry:`	`entry:`
	`LDI 0x0c000010,R0`
	`LDI dev.scope.cpu,R1`
	`STO R0,(R1)`
	`;`
`MOV top_of_stack(PC),uSP`	`MOV top_of_stack(PC),uSP`
`MOV entry(PC),uR12`	`MOV entry(PC),uR12`
`; Store our tick counter in R1`	`; Store our tick counter in R1`
`LDI sys.ctr.mtask,R1`	`LDI sys.ctr.mtask,R1`
`; And start with our counter cleared at zero`	`; And start with our counter cleared at zero`
Line 178...	Line 186...
`#endif`	`#endif`
`; Read the tick counter back out`	`; Read the tick counter back out`
`LOD (R1),R0`	`LOD (R1),R0`
`HALT ; Stop the CPU--We're done!!!!!!!`	`HALT ; Stop the CPU--We're done!!!!!!!`

	`//`
`// typedef enum { Ident_1, Ident_2, Ident_3, Ident_4, Ident_5 } test_enum;`	`// typedef enum { Ident_1, Ident_2, Ident_3, Ident_4, Ident_5 } test_enum;`
`// typedef enum { false, true } bool;`	`// typedef enum { false, true } bool;`

`// typedef int Arr_1_Dim[50];`	`// typedef int Arr_1_Dim[50];`
`// typedef int Arr_2_Dim[50][50];`	`// typedef int Arr_2_Dim[50][50];`
Line 191...	Line 200...
`discr equ 1`	`discr equ 1`
`variant.var_1.enum_comp equ 2`	`variant.var_1.enum_comp equ 2`
`variant.var_1.int_comp equ 3`	`variant.var_1.int_comp equ 3`
`variant.var_1.str_comp equ 4`	`variant.var_1.str_comp equ 4`

`gbl_arr_1:`
`fill 50,0`
`gbl_arr_2:`
`fill 2500,0`
`gbl_ch:`
`word 0`
`gbl_ch_2:`
`word 0`
`gbl_bool:`
`word 0`
`gbl_int:`
`word 0`
`gbl_ptr:`
`word 0`

`some_string:`
`word 'D','H','R','Y','S','T','O','N','E',' '`
`word 'P','R','O','G','R','A','M',',',' '`
`word 'S','O','M','E',' ','S','T','R','I','N','G'`
`word 0`

`first_string:`
`word 'D','H','R','Y','S','T','O','N','E',' '`
`word 'P','R','O','G','R','A','M',','`
`word ' ','1','\'','S','T'`
`word ' ','S','T','R','I','N','G'`
`word 0`

`second_string:`
`word 'D','H','R','Y','S','T','O','N','E',' '`
`word 'P','R','O','G','R','A','M',',',' '`
`word '2','\'','N','D',' ','S','T','R','I','N','G'`
`word 0`

`third_string:`
`word 'D','H','R','Y','S','T','O','N','E',' '`
`word 'P','R','O','G','R','A','M',',',' '`
`word '3','\'','R','D',' ','S','T','R','I','N','G'`
`word 0`

`// Arr_1_Dim gbl_arr_1;`
`// Arr_2_Dim gbl_arr_2;`
`// char gbl_ch, gbl_ch_2;`
`// bool gbl_bool;`
`// int gbl_int;`
`// RECP gbl_ptr;`

`//char lcl_strcpy(char d, char *s) {`	`//char lcl_strcpy(char d, char *s) {`
`// char *cpd = d, ch;`	`// char *cpd = d, ch;`
`//`	`//`
`// do{`	`// do{`
Line 290...	Line 253...
`CMP 0,R2`	`CMP 0,R2`
`STO.NZ R2,(R0)`	`STO.NZ R2,(R0)`
`CMP.NZ 0,R3`	`CMP.NZ 0,R3`
`STO.NZ R3,1(R0)`	`STO.NZ R3,1(R0)`
`CMP.NZ 0,R4`	`CMP.NZ 0,R4`
`STO.NZ R4,1(R0)`	`STO.NZ R4,2(R0)`
`CMP.NZ 0,R5`	`CMP.NZ 0,R5`
`STO.NZ R5,1(R0)`	`STO.NZ R5,3(R0)`

`LOD (SP),R2`	`LOD (SP),R2`
`LOD 1(SP),R3`	`LOD 1(SP),R3`
`LOD 2(SP),R4`	`LOD 2(SP),R4`
`LOD 3(SP),R5`	`LOD 3(SP),R5`
`ADD 4,SP`	`ADD 4,SP`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R2`
	`HALT.LT`
	`#endif`
`JMP R2`	`JMP R2`
`NOP`

`#else`	`#else`
`lcl_strcpy:`	`lcl_strcpy:`
`; R0 = d`	`; R0 = d`
`; R1 = s`	`; R1 = s`
Line 343...	Line 309...
`BRA copy_next_char`	`BRA copy_next_char`
`#endif`	`#endif`
`lcl_strcpy_end_of_loop:`	`lcl_strcpy_end_of_loop:`
`LOD (SP),R2`	`LOD (SP),R2`
`ADD 1,SP`	`ADD 1,SP`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R2`
	`BUSY.LT`
	`#endif`
`JMP R2`	`JMP R2`
`#endif`	`#endif`

`//int lcl_strcmp(char s1, char s2) {`	`//int lcl_strcmp(char s1, char s2) {`
`// char a, b;`	`// char a, b;`
Line 378...	Line 348...
`LOD (R1),R6`	`LOD (R1),R6`
`LOD 1(R1),R7`	`LOD 1(R1),R7`
`LOD 2(R1),R8`	`LOD 2(R1),R8`
`LOD 3(R1),R9`	`LOD 3(R1),R9`
`;`	`;`
	`;`
`CMP 0,R2`	`CMP 0,R2`
`CMP.NZ 0,R3`	`CMP.NZ 0,R3`
`CMP.NZ 0,R4`	`CMP.NZ 0,R4`
`CMP.NZ 0,R5`	`CMP.NZ 0,R5`
`BZ strcmp_end_loop`	`BZ strcmp_end_loop`
Line 430...	Line 401...
`LOD 4(SP),R6`	`LOD 4(SP),R6`
`LOD 5(SP),R7`	`LOD 5(SP),R7`
`LOD 6(SP),R8`	`LOD 6(SP),R8`
`LOD 7(SP),R9`	`LOD 7(SP),R9`
`ADD 8,SP`	`ADD 8,SP`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R2`
	`BUSY.LT`
	`#endif`
`JMP R2`	`JMP R2`
`NOP`

`#else`	`#else`
`lcl_strcmp:`	`lcl_strcmp:`
`SUB 2,SP`	`SUB 2,SP`
`STO R2,(SP)`	`STO R2,(SP)`
Line 497...	Line 471...
`MOV R2,R0`	`MOV R2,R0`

`LOD (SP),R2`	`LOD (SP),R2`
`LOD 1(SP),R3`	`LOD 1(SP),R3`
`ADD 2,SP`	`ADD 2,SP`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R2`
	`BUSY.LT`
	`#endif`
`JMP R2`	`JMP R2`
`#endif`	`#endif`


`//test_enum func_1(char ch_1, char ch_2) {`	`//test_enum func_1(char ch_1, char ch_2) {`
Line 530...	Line 508...
`CLR.NZ R0`	`CLR.NZ R0`
`STO.Z R2,gbl_ch(R12)`	`STO.Z R2,gbl_ch(R12)`
`LDILO.Z 1,R0`	`LDILO.Z 1,R0`
`LOD (SP),R2`	`LOD (SP),R2`
`ADD 1,SP`	`ADD 1,SP`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R2`
	`BUSY.LT`
	`#endif`
`JMP R2`	`JMP R2`
`#endif`	`#endif`

`//bool func_2(char str_1, char str_2) {`	`//bool func_2(char str_1, char str_2) {`
`// int lcl_int;`	`// int lcl_int;`
Line 560...	Line 542...
`// }`	`// }`
`//}`	`//}`
`func_2:`	`func_2:`
`;`	`;`
`SUB 6,SP`	`SUB 6,SP`
`STO R2,(SP)`	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R2`
	`BUSY.LT`
	`#endif`
	`STO R2,(SP) ; SP = 0x08daf`
`STO R3,1(SP)`	`STO R3,1(SP)`
`STO R4,2(SP)`	`STO R4,2(SP)`
`STO R5,3(SP)`	`STO R5,3(SP)`
`STO R6,4(SP)`	`STO R6,4(SP)`
`STO R7,5(SP)`	`STO R7,5(SP)`
Line 648...	Line 634...
`LOD 2(SP),R4`	`LOD 2(SP),R4`
`LOD 3(SP),R5`	`LOD 3(SP),R5`
`LOD 4(SP),R6`	`LOD 4(SP),R6`
`LOD 5(SP),R7`	`LOD 5(SP),R7`
`ADD 6,SP`	`ADD 6,SP`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R2`
	`BUSY.LT`
	`#endif`
`JMP R2`	`JMP R2`
`NOP`

`//bool func_3(test_enum a) {`	`//bool func_3(test_enum a) {`
`// test_enum lcl_enum;`	`// test_enum lcl_enum;`
`//`	`//`
`// lcl_enum = a;`	`// lcl_enum = a;`
Line 669...	Line 658...
`; R0 = a`	`; R0 = a`
`; R1 - available`	`; R1 - available`
`CMP 2,R0`	`CMP 2,R0`
`CLR R0 ; CLR Doesn't set flags`	`CLR R0 ; CLR Doesn't set flags`
`LDILO.Z 1,R0`	`LDILO.Z 1,R0`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R1`
	`BUSY.LT`
	`#endif`
`JMP R1`	`JMP R1`
`#endif`	`#endif`


`// void proc_6(test_enum ev, test_enum *ep) {`	`// void proc_6(test_enum ev, test_enum *ep) {`
Line 731...	Line 724...
`#endif`	`#endif`
`STO.Z R1,(R3)`	`STO.Z R1,(R3)`
`#else`	`#else`
`CMP 2,R0`	`CMP 2,R0`
`LDI 3,R1`	`LDI 3,R1`
`#ifdef SKIP_SHORT_CIRCUITS`	`#ifndef SKIP_SHORT_CIRCUITS`
`BUSY.NZ`	`BUSY.NZ`
`#endif`	`#endif`
`STO.NZ R1,(R3)`	`STO.NZ R1,(R3)`
`#endif`	`#endif`

Line 769...	Line 762...
`LDI 1,R1 // Executed, if done properly`	`LDI 1,R1 // Executed, if done properly`
`STO R1,(R3)`	`STO R1,(R3)`
`BRA proc_6_end_of_case`	`BRA proc_6_end_of_case`
`proc_6_case_not_two:`	`proc_6_case_not_two:`
`#ifndef SKIP_SHORT_CIRCUITS`	`#ifndef SKIP_SHORT_CIRCUITS`
`BUSY`	`NOOP ;;;;;;;; TODO This fails--needs the NOOP`
	`BUSY ;;;;;;;; TODO so as not to do the BUSY`
`#endif`	`#endif`
`CMP 4,R2`	`CMP 4,R2`
`BNZ proc_6_case_not_four`	`BNZ proc_6_case_not_four`
`LDI 2,R1`	`LDI 2,R1`
`STO R1,(R3)`	`STO R1,(R3)`
`// BRA proc_6_end_of_case`	`// BRA proc_6_end_of_case`
`proc_6_case_not_four:`	`proc_6_case_not_four:`
`proc_6_end_of_case:`	`proc_6_end_of_case:`
`LOD (SP),R2`	`LOD (SP),R2`
`LOD 1(SP),R3`	`LOD 1(SP),R3`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R2 ; TODO This fails, even when the address`
	`BUSY.LT`
	`#endif`
`ADD 2,SP`	`ADD 2,SP`
`JMP R2`	`JMP R2`
`NOP`

`// void proc_7(int a, int b, int *c) {`	`// void proc_7(int a, int b, int *c) {`
`// int lcl;`	`// int lcl;`
`//`	`//`
`// lcl = a + 2;`	`// lcl = a + 2;`
Line 796...	Line 793...
`#ifdef NO_INLINE`	`#ifdef NO_INLINE`
`proc_7:`	`proc_7:`
`ADD 2+R0,R1`	`ADD 2+R0,R1`
`STO R1,(R2)`	`STO R1,(R2)`

	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R3`
	`BUSY.LT`
	`#endif`
`JMP R3`	`JMP R3`
`#endif`	`#endif`

`// int a[50];`	`// int a[50];`
`// int b[50][50];`	`// int b[50][50];`
Line 869...	Line 870...

`LOD (SP),R4`	`LOD (SP),R4`
`LOD 1(SP),R5`	`LOD 1(SP),R5`
`LOD 2(SP),R6`	`LOD 2(SP),R6`
`ADD 3,SP`	`ADD 3,SP`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R4`
	`BUSY.LT`
	`#endif`
`JMP R4`	`JMP R4`

`// void proc_5(void) {`	`// void proc_5(void) {`
`// gbl_ch = 'A';`	`// gbl_ch = 'A';`
`// gbl_bool = false;`	`// gbl_bool = false;`
Line 953...	Line 958...
`;`	`;`
`LOD (SP),R1`	`LOD (SP),R1`
`LOD 1(SP),R2`	`LOD 1(SP),R2`
`LOD 2(SP),R3`	`LOD 2(SP),R3`
`ADD 3,SP`	`ADD 3,SP`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R1`
	`BUSY.LT`
	`#endif`
`JMP R1`	`JMP R1`
`NOP`

`// void proc_2(int *a) {`	`// void proc_2(int *a) {`
`// int lcl_int;`	`// int lcl_int;`
`// test_enum lcl_enum;`	`// test_enum lcl_enum;`
`//`	`//`
Line 1014...	Line 1022...
`LOD 2(SP),R3`	`LOD 2(SP),R3`
`LOD 3(SP),R4`	`LOD 3(SP),R4`
`LOD 4(SP),R5`	`LOD 4(SP),R5`
`LOD 5(SP),R6`	`LOD 5(SP),R6`
`ADD 6,SP`	`ADD 6,SP`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R1`
	`BUSY.LT`
	`#endif`
`JMP R1`	`JMP R1`
`NOP`

`//void proc_1 (RECP a) {`	`//void proc_1 (RECP a) {`
`// RECP nxt = a->ptr_comp;`	`// RECP nxt = a->ptr_comp;`
`//`	`//`
`// // structassign(a->ptr_comp, gbl_ptr);`	`// // structassign(a->ptr_comp, gbl_ptr);`
Line 1059...	Line 1070...
`; R12 = GBL`	`; R12 = GBL`
`; R13 = SP`	`; R13 = SP`
`MOV R0,R9`	`MOV R0,R9`
`LOD ptr_comp(R9),R4`	`LOD ptr_comp(R9),R4`
`#ifndef SKIP_SHORT_CIRCUITS`	`#ifndef SKIP_SHORT_CIRCUITS`
`TST -1,R4`	`TST -1,R4 ; R4 = 0x100e9f`
`BUSY.Z`	`BUSY.Z`
`CMP PC,R9`	`CMP PC,R9 ; R9 = 0x100ec2`
`BUSY.LT`	`BUSY.LT`
`#endif`	`#endif`
`MOV R9,R6`	`MOV R9,R6`
`LOD gbl_ptr(R12),R7`	`LOD gbl_ptr(R12),R7 ; (0x100a04) -> 0x100ec2`
	`; BUSY ; R7 = 0x0100ec2`

`#ifndef SKIP_SHORT_CIRCUITS`	`#ifndef SKIP_SHORT_CIRCUITS`
`LOD variant.var_1.enum_comp(R7), R0`	`LOD variant.var_1.enum_comp(R7), R0`
`CMP 2,R0`	`CMP 2,R0 ; R0 = 0`
`BUSY.NZ`	`BUSY.NZ ; TODO Fails here`
`#endif`	`#endif`

`#ifdef NO_LOOP_UNROLLING`	`#ifdef NO_LOOP_UNROLLING`
`LDI 35,R5`	`LDI 35,R5`
`proc_1_assign_loop_1:`	`proc_1_assign_loop_1:`
Line 1122...	Line 1134...
`#endif`	`#endif`

`LDI 5,R5`	`LDI 5,R5`
`STO R5,variant.var_1.int_comp(R9)`	`STO R5,variant.var_1.int_comp(R9)`
`STO R5,variant.var_1.int_comp(R4)`	`STO R5,variant.var_1.int_comp(R4)`
`MOV ptr_comp(R4),R0`	`MOV ptr_comp(R4),R0 ; R4 = 0x8e41, ptr_comp(R4)=R4`
`MOV __HERE__+2(PC),R1`	`MOV __HERE__+2(PC),R1`
`BRA proc_3 ; Uses R0 and R1`	`BRA proc_3 ; Uses R0 and R1`

`LOD discr(R4),R5`	`LOD discr(R4),R5`
`CMP 0,R5`	`CMP 0,R5`
Line 1190...	Line 1202...
`#ifndef NO_LOOP_UNROLLING`	`#ifndef NO_LOOP_UNROLLING`
`LOD 9(SP),R10`	`LOD 9(SP),R10`
`LOD 10(SP),R11`	`LOD 10(SP),R11`
`#endif`	`#endif`
`ADD 11,SP`	`ADD 11,SP`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R1`
	`BUSY.LT`
	`#endif`
`JMP R1 // Jumps to wrong address ??`	`JMP R1 // Jumps to wrong address ??`
`NOP`

`// void dhrystone(void) {`	`// void dhrystone(void) {`
`// int lcl_int_1, lcl_int_2, lcl_int_3, index, number_of_runs = 500;`	`// int lcl_int_1, lcl_int_2, lcl_int_3, index, number_of_runs = 500;`
`// test_enum lcl_enum;`	`// test_enum lcl_enum;`
`// char lcl_str_1[30], lcl_str_2[30], ch_index;`	`// char lcl_str_1[30], lcl_str_2[30], ch_index;`
Line 1365...	Line 1380...
`CMP R6,R5`	`CMP R6,R5`
`BGE dhrystone_end_while_loop`	`BGE dhrystone_end_while_loop`
`dhrystone_while_loop:`	`dhrystone_while_loop:`
`// lcl_int_3 = 5 * lcl_int_1 - lcl_int_2;`	`// lcl_int_3 = 5 * lcl_int_1 - lcl_int_2;`
`MOV R5,R7`	`MOV R5,R7`
`MPYS 5,R7`	`LDI 5,R0`
	`MPYS R0,R7`
`SUB R6,R7`	`SUB R6,R7`
`STO R7,lcl_int_3(SP)`	`STO R7,lcl_int_3(SP)`
`#ifndef SKIP_SHORT_CIRCUITS`	`#ifndef SKIP_SHORT_CIRCUITS`
`CMP 7,R7`	`CMP 7,R7`
`BUSY.NZ`	`BUSY.NZ`
Line 1414...	Line 1430...
`MOV R6,R3`	`MOV R6,R3`
`MOV __HERE__+2(PC),R4`	`MOV __HERE__+2(PC),R4`
`BRA proc_8`	`BRA proc_8`
`// proc_1(gbl_ptr);`	`// proc_1(gbl_ptr);`
`LOD gbl_ptr(PC),R0`	`LOD gbl_ptr(PC),R0`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`LOD variant.var_1.enum_comp(R0), R1`
	`CMP 2,R1 ; R0 = 0`
	`BUSY.NZ ; TODO Fails here`
	`#endif`
`MOV __HERE__+2(PC),R1`	`MOV __HERE__+2(PC),R1`
`BRA proc_1`	`BRA proc_1`
`//`	`//`
`// for(ch_index='A'; ch_index <= gbl_ch_2; ch_index++) {`	`// for(ch_index='A'; ch_index <= gbl_ch_2; ch_index++) {`
`LDI 'A',R7`	`LDI 'A',R7`
Line 1498...	Line 1519...
`BRA lib_divs`	`BRA lib_divs`
`#else`	`#else`
`LDI 9,R0`	`LDI 9,R0`
`#endif`	`#endif`
`#endif`	`#endif`
`STO R0,lcl_int_1(SP)`	`STO R0,lcl_int_1(SP) ;;; TODO FAILS HERE (Watched it fail!)`
`// lcl_int_2 = 7 * ( lcl_int_2 - lcl_int_3) - lcl_int_1;`	`// lcl_int_2 = 7 * ( lcl_int_2 - lcl_int_3) - lcl_int_1;`
`LOD lcl_int_3(SP),R2`	`LOD lcl_int_3(SP),R2`
`SUB R2,R6`	`SUB R2,R6`
`MPYS 7,R6`	`MPYS 7,R6`
`SUB R0,R6`	`SUB R0,R6`
`// proc_2(&lcl_int_1);`	`// proc_2(&lcl_int_1);`
`#ifndef SKIP_SHORT_CIRCUITS`	`#ifndef SKIP_SHORT_CIRCUITS`
`LOD lcl_int_1(SP),R0`	`LOD lcl_int_1(SP),R0`
`CMP 1,R0`	`CMP 1,R0`
`BUSY.NZ`	`CMP.Z 13,R6`
`CMP 13,R6`	`LOD.Z lcl_int_3(SP),R0`
`BUSY.NZ`	`CMP.Z 7,R0`
`LOD lcl_int_3(SP),R0`	`BZ dhrystone_triple_test_still_good`
`CMP 7,R0`	`BUSY`
`BUSY.NZ`	`dhrystone_triple_test_still_good:`
`#endif`	`#endif`
`MOV lcl_int_1(SP),R0`	`MOV lcl_int_1(SP),R0`
`MOV __HERE__+2(PC),R1`	`MOV __HERE__+2(PC),R1`
`BRA proc_2`	`BRA proc_2`
`#ifndef SKIP_SHORT_CIRCUITS`	`#ifndef SKIP_SHORT_CIRCUITS`
Line 1546...	Line 1567...
`LOD 10(SP),R10`	`LOD 10(SP),R10`
`LOD 11(SP),R11`	`LOD 11(SP),R11`
`;`	`;`
`ADD 12+RECSIZE+RECSIZE+30+30+3,SP`	`ADD 12+RECSIZE+RECSIZE+30+30+3,SP`
`; Return from subroutine`	`; Return from subroutine`
	`#ifndef SKIP_SHORT_CIRCUITS`
	`CMP LOAD_ADDRESS,R0`
	`BUSY.LT`
	`#endif`
`JMP R0`	`JMP R0`
`#else`	`#else`
`LDI 0,CC`	`LDI 0,CC`
`NOP`	`NOP`
`NOP`	`NOP`
`BUSY`	`BUSY`
`#endif`	`#endif`
	`gbl_arr_1:`
	`fill 50,0`
	`gbl_arr_2:`
	`fill 2500,0`
	`gbl_ch:`
	`word 0`
	`gbl_ch_2:`
	`word 0`
	`gbl_bool:`
	`word 0`
	`gbl_int:`
	`word 0`
	`gbl_ptr:`
	`word 0`

	`some_string:`
	`word 'D','H','R','Y','S','T','O','N','E',' '`
	`word 'P','R','O','G','R','A','M',',',' '`
	`word 'S','O','M','E',' ','S','T','R','I','N','G'`
	`word 0`

	`first_string:`
	`word 'D','H','R','Y','S','T','O','N','E',' '`
	`word 'P','R','O','G','R','A','M',','`
	`word ' ','1','\'','S','T'`
	`word ' ','S','T','R','I','N','G'`
	`word 0`

	`second_string:`
	`word 'D','H','R','Y','S','T','O','N','E',' '`
	`word 'P','R','O','G','R','A','M',',',' '`
	`word '2','\'','N','D',' ','S','T','R','I','N','G'`
	`word 0`

	`third_string:`
	`word 'D','H','R','Y','S','T','O','N','E',' '`
	`word 'P','R','O','G','R','A','M',',',' '`
	`word '3','\'','R','D',' ','S','T','R','I','N','G'`
	`word 0`

	`// Arr_1_Dim gbl_arr_1;`
	`// Arr_2_Dim gbl_arr_2;`
	`// char gbl_ch, gbl_ch_2;`
	`// bool gbl_bool;`
	`// int gbl_int;`
	`// RECP gbl_ptr;`

`;`	`;`

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