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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
[/] [zipcpu/] [trunk/] [bench/] [cpp/] [memsim.cpp] - Diff between revs 2 and 36
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| Rev 2 |
Rev 36 |
| Line 77... |
Line 77... |
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for(; nr<m_len; nr++)
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for(; nr<m_len; nr++)
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m_mem[nr] = 0l;
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m_mem[nr] = 0l;
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}
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}
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void MEMSIM::apply(const unsigned char wb_cyc,
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void MEMSIM::apply(const unsigned int clk, const unsigned char wb_cyc,
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const unsigned char wb_stb, const unsigned char wb_we,
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const unsigned char wb_stb, const unsigned char wb_we,
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const BUSW wb_addr, const BUSW wb_data,
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const BUSW wb_addr, const BUSW wb_data,
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unsigned char &o_ack, unsigned char &o_stall, BUSW &o_data) {
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unsigned char &o_ack, unsigned char &o_stall, BUSW &o_data) {
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if ((wb_cyc)&&(wb_stb)) {
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if ((wb_cyc)&&(wb_stb)&&(clk)) {
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if (wb_we)
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if (wb_we)
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m_mem[wb_addr & m_mask] = wb_data;
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m_mem[wb_addr & m_mask] = wb_data;
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o_ack = 1;
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o_ack = 1;
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o_stall= 0;
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o_stall= 0;
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o_data = m_mem[wb_addr & m_mask];
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o_data = m_mem[wb_addr & m_mask];
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| Line 93... |
Line 93... |
/*
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/*
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printf("MEMBUS -- ACK %s 0x%08x - 0x%08x\n",
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printf("MEMBUS -- ACK %s 0x%08x - 0x%08x\n",
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(wb_we)?"WRITE":"READ",
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(wb_we)?"WRITE":"READ",
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wb_addr, o_data);
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wb_addr, o_data);
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*/
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*/
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} else {
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} else if (clk) {
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o_ack = 0;
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o_ack = 0;
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o_stall = 0;
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o_stall = 0;
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}
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}
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}
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}
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