| Line 432... |
Line 432... |
|
|
showreg(ln, 0, "sR12", 12, (m_cursor==24));
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showreg(ln, 0, "sR12", 12, (m_cursor==24));
|
showreg(ln,20, "sSP ", 13, (m_cursor==25));
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showreg(ln,20, "sSP ", 13, (m_cursor==25));
|
|
|
unsigned int cc = m_state.m_sR[14];
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unsigned int cc = m_state.m_sR[14];
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if (true) {
|
if (false) {
|
mvprintw(ln,40, "%ssCC : 0x%08x",
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mvprintw(ln,40, "%ssCC : 0x%08x",
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(m_cursor==26)?">":" ", cc);
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(m_cursor==26)?">":" ", cc);
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} else {
|
} else {
|
mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
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mvprintw(ln,40, "%ssCC :%s%s%s%s%s%s%s",
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(m_cursor==26)?">":" ",
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(m_cursor==26)?">":" ",
|
| Line 573... |
Line 573... |
// #define OPT_PIPELINED_BUS_ACCESS
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// #define OPT_PIPELINED_BUS_ACCESS
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#ifdef OPT_PIPELINED_BUS_ACCESS
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
printw(" %x%x%c%c",
|
printw(" %x%x%c%c",
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(m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
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(m_core->v__DOT__thecpu__DOT__domem__DOT__wraddr),
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(m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
|
(m_core->v__DOT__thecpu__DOT__domem__DOT__rdaddr),
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(m_core->v__DOT__thecpu__DOT__op_pipe)?'P':'-',
|
(m_core->v__DOT__thecpu__DOT__r_op_pipe)?'P':'-',
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(mem_pipe_stalled())?'S':'-'); ln++;
|
(mem_pipe_stalled())?'S':'-'); ln++;
|
#else
|
#else
|
ln++;
|
ln++;
|
#endif
|
#endif
|
|
|
| Line 603... |
Line 603... |
|
|
(mem_stalled()),
|
(mem_stalled()),
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
|
(m_core->v__DOT__thecpu__DOT__opvalid_mem),
|
(m_core->v__DOT__thecpu__DOT__master_ce),
|
(m_core->v__DOT__thecpu__DOT__master_ce),
|
(mem_pipe_stalled()),
|
(mem_pipe_stalled()),
|
(!m_core->v__DOT__thecpu__DOT__op_pipe),
|
(!m_core->v__DOT__thecpu__DOT__r_op_pipe),
|
(m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
|
(m_core->v__DOT__thecpu__DOT__domem__DOT__cyc)
|
);
|
);
|
printw(" op_pipe = %d", m_core->v__DOT__thecpu__DOT__dcd_pipe);
|
printw(" op_pipe = %d", m_core->v__DOT__thecpu__DOT__dcd_pipe);
|
// mvprintw(4,4,"r_dcdI = 0x%06x",
|
// mvprintw(4,4,"r_dcdI = 0x%06x",
|
// (m_core->v__DOT__thecpu__DOT__dcdI)&0x0ffffff);
|
// (m_core->v__DOT__thecpu__DOT__dcdI)&0x0ffffff);
|
| Line 1343... |
Line 1343... |
op_gie = m_core->v__DOT__thecpu__DOT__op_gie;
|
op_gie = m_core->v__DOT__thecpu__DOT__op_gie;
|
|
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
#ifdef OPT_PIPELINED_BUS_ACCESS
|
//a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
|
//a = m_core->v__DOT__thecpu__DOT__mem_pipe_stalled;
|
a = mem_pipe_stalled();
|
a = mem_pipe_stalled();
|
b = (!m_core->v__DOT__thecpu__DOT__op_pipe)&&(mem_busy());
|
b = (!m_core->v__DOT__thecpu__DOT__r_op_pipe)&&(mem_busy());
|
#else
|
#else
|
a = false;
|
a = false;
|
b = false;
|
b = false;
|
#endif
|
#endif
|
d = ((wr_write_pc)||(wr_write_cc));
|
d = ((wr_write_pc)||(wr_write_cc));
|
| Line 1385... |
Line 1385... |
bool test_failure(void) {
|
bool test_failure(void) {
|
if (m_core->v__DOT__thecpu__DOT__sleep)
|
if (m_core->v__DOT__thecpu__DOT__sleep)
|
return 0;
|
return 0;
|
else if (m_core->v__DOT__thecpu__DOT__gie)
|
else if (m_core->v__DOT__thecpu__DOT__gie)
|
return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x7bc3dfff);
|
return (m_mem[m_core->v__DOT__thecpu__DOT__upc] == 0x7bc3dfff);
|
else
|
else if (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7883ffff)
|
|
return true; // ADD to PC instruction
|
|
else // MOV to PC instruction
|
return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7bc3dfff);
|
return (m_mem[m_core->v__DOT__thecpu__DOT__ipc] == 0x7bc3dfff);
|
/*
|
/*
|
return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
|
return ((m_core->v__DOT__thecpu__DOT__alu_pc_valid)
|
&&(m_mem[alu_pc()] == 0x2f0f7fff)
|
&&(m_mem[alu_pc()] == 0x2f0f7fff)
|
&&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
|
&&(!m_core->v__DOT__thecpu__DOT__clear_pipeline));
|
