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% \graphicspath{{../gfx}}
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% \graphicspath{{../gfx}}
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\project{Zip CPU}
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\project{Zip CPU}
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\title{Specification}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) opencores.org}
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\email{dgisselq (at) opencores.org}
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\revision{Rev.~0.7}
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\revision{Rev.~0.8}
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\definecolor{webred}{rgb}{0.5,0,0}
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\definecolor{webred}{rgb}{0.5,0,0}
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\definecolor{webgreen}{rgb}{0,0.4,0}
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\definecolor{webgreen}{rgb}{0,0.4,0}
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\usepackage[dvips,ps2pdf,colorlinks=true,
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\usepackage[dvips,ps2pdf,colorlinks=true,
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anchorcolor=black,pdfpagelabels,hypertexnames,
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anchorcolor=black,pdfpagelabels,hypertexnames,
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pdfauthor={Dan Gisselquist},
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pdfauthor={Dan Gisselquist},
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You should have received a copy of the GNU General Public License along
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You should have received a copy of the GNU General Public License along
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with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a
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with this program. If not, see \hbox{<http://www.gnu.org/licenses/>} for a
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copy.
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copy.
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\end{license}
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\end{license}
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\begin{revisionhistory}
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\begin{revisionhistory}
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0.8 & 1/28/2016 & Gisselquist & Reduced complexity early branching \\\hline
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0.7 & 12/22/2015 & Gisselquist & New Instruction Set Architecture \\\hline
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0.7 & 12/22/2015 & Gisselquist & New Instruction Set Architecture \\\hline
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0.6 & 11/17/2015 & Gisselquist & Added graphics to illustrate pipeline discussion.\\\hline
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0.6 & 11/17/2015 & Gisselquist & Added graphics to illustrate pipeline discussion.\\\hline
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0.5 & 9/29/2015 & Gisselquist & Added pipelined memory access discussion.\\\hline
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0.5 & 9/29/2015 & Gisselquist & Added pipelined memory access discussion.\\\hline
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0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline
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0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline
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0.3 & 8/22/2015 & Gisselquist & First completed draft\\\hline
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0.3 & 8/22/2015 & Gisselquist & First completed draft\\\hline
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& Absolute value, depends upon derived NEG.\\\hline
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& Absolute value, depends upon derived NEG.\\\hline
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\parbox[t]{1.4in}{\tt ADD Ra,Rx\\ADDC Rb,Ry}
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\parbox[t]{1.4in}{\tt ADD Ra,Rx\\ADDC Rb,Ry}
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& \parbox[t]{1.5in}{\tt Add Ra,Rx\\ADD.C \$1,Ry\\Add Rb,Ry}
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& \parbox[t]{1.5in}{\tt Add Ra,Rx\\ADD.C \$1,Ry\\Add Rb,Ry}
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& Add with carry \\\hline
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& Add with carry \\\hline
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{\tt BRA.Cond +/-\$Addr}
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{\tt BRA.Cond +/-\$Addr}
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& \hbox{\tt MOV.cond \$Addr+PC,PC}
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& \hbox{\tt ADD.cond \$Addr+PC,PC}
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& Branch or jump on condition. Works for 13--bit
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& Branch or jump on condition. Works for 18--bit
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signed address offsets.\\\hline
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signed address offsets.\\\hline
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{\tt BRA.Cond +/-\$Addr}
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{\tt BRA.Cond +/-\$Addr}
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& \parbox[t]{1.5in}{\tt LDI \$Addr,Rx \\ ADD.cond Rx,PC}
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& \parbox[t]{1.5in}{\tt LDI \$Addr,Rx \\ ADD.cond Rx,PC}
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& Branch/jump on condition. Works for 23 bit address offsets, but
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& Branch/jump on condition. Works for 23 bit address offsets, but
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costs a register and an extra instruction. With LDIHI and LDILO
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costs a register and an extra instruction. With LDIHI and LDILO
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this can be made to work anywhere in the 32-bit address space, but yet
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this can be made to work anywhere in the 32-bit address space, but yet
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cost an additional instruction still. \\\hline
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cost an additional instruction still. \\\hline
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{\tt BNC PC+\$Addr}
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{\tt BNC PC+\$Addr}
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& \parbox[t]{1.5in}{\tt Test \$Carry,CC \\ MOV.Z PC+\$Addr,PC}
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& \parbox[t]{1.5in}{\tt Test \$Carry,CC \\ ADD.Z PC+\$Addr,PC}
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& Example of a branch on an unsupported
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& Example of a branch on an unsupported
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condition, in this case a branch on not carry \\\hline
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condition, in this case a branch on not carry \\\hline
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{\tt BUSY } & {\tt MOV \$-1(PC),PC} & Execute an infinite loop \\\hline
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{\tt BUSY } & {\tt ADD \$-1,PC} & Execute an infinite loop \\\hline
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{\tt CLRF.NZ Rx }
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{\tt CLRF.NZ Rx }
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& {\tt XOR.NZ Rx,Rx}
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& {\tt XOR.NZ Rx,Rx}
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& Clear Rx, and flags, if the Z-bit is not set \\\hline
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& Clear Rx, and flags, if the Z-bit is not set \\\hline
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{\tt CLR Rx }
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{\tt CLR Rx }
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& {\tt LDI \$0,Rx}
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& {\tt LDI \$0,Rx}
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mode this is simply a wait until interrupt instruction. \\\hline
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mode this is simply a wait until interrupt instruction. \\\hline
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{\tt INT } & {\tt LDI \$0,CC} & This is also known as a trap instruction\\\hline
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{\tt INT } & {\tt LDI \$0,CC} & This is also known as a trap instruction\\\hline
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{\tt IRET}
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{\tt IRET}
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& {\tt OR \$GIE,CC}
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& {\tt OR \$GIE,CC}
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& Also known as an RTU instruction (Return to Userspace) \\\hline
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& Also known as an RTU instruction (Return to Userspace) \\\hline
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{\tt JMP R6+\$Addr}
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{\tt JMP R6+\$Offset}
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& {\tt MOV \$Addr(R6),PC}
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& {\tt MOV \$Offset(R6),PC}
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& \\\hline
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& \\\hline
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{\tt LJMP \$Addr}
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{\tt LJMP \$Addr}
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& \parbox[t]{1.5in}{\tt LOD (PC),PC \\ {\em Address }}
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& \parbox[t]{1.5in}{\tt LOD (PC),PC \\ {\em Address }}
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& Although this only works for an unconditional jump, and it only
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& Although this only works for an unconditional jump, and it only
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works in a Von Neumann architecture, this instruction combination makes
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works in a Von Neumann architecture, this instruction combination makes
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for a nice combination that can be adjusted by a linker at a later
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for a nice combination that can be adjusted by a linker at a later
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time.\\\hline
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time.\\\hline
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{\tt JSR PC+\$Addr }
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{\tt JSR PC+\$Offset }
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& \parbox[t]{1.5in}{\tt MOV \$1+PC,R0 \\ MOV \$addr+PC,PC}
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& \parbox[t]{1.5in}{\tt MOV \$1+PC,R0 \\ ADD \$Offset,PC}
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& This is similar to the jump and link instructions from other
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& This is similar to the jump and link instructions from other
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architectures, save only that it requires a specific link
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architectures, save only that it requires a specific link
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instruction, also known as the {\tt MOV} instruction on the
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instruction, also known as the {\tt MOV} instruction on the
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left.\\\hline
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left.\\\hline
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\end{tabular}
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\end{tabular}
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{\tt IA}. Therefore, the pipeline needs to be cleared and reloaded.
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{\tt IA}. Therefore, the pipeline needs to be cleared and reloaded.
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Given that there are five stages to the pipeline, that accounts
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Given that there are five stages to the pipeline, that accounts
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for the four stalls. (Were the {\tt pipefetch} cache chosen, there would
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for the four stalls. (Were the {\tt pipefetch} cache chosen, there would
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be another stall internal to the {\tt pipefetch} cache.)
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be another stall internal to the {\tt pipefetch} cache.)
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The Zip CPU handles {\tt MOV \$X(PC),PC}, {\tt ADD \$X,PC}, and
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The Zip CPU handles the {\tt ADD \$X,PC} and
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{\tt LDI \$X,PC} instructions specially, however. These instructions, when
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{\tt LDI \$X,PC} instructions specially, however. These instructions, when
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not conditioned on the flags, can execute with only a single stall cycle,
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not conditioned on the flags, can execute with only a single stall cycle,
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such as is shown in Fig.~\ref{fig:branch}.\footnote{Note that when using the
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such as is shown in Fig.~\ref{fig:branch}.\footnote{Note that when using the
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{\tt pipefetch} cache, this requires an additional stall cycle due to that
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{\tt pipefetch} cache, this requires an additional stall cycle due to that
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cache's implementation.}
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cache's implementation.}
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