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% \graphicspath{{../gfx}}
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\project{Zip CPU}
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\project{Zip CPU}
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\title{Specification}
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\title{Specification}
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\author{Dan Gisselquist, Ph.D.}
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\author{Dan Gisselquist, Ph.D.}
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\email{dgisselq (at) opencores.org}
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\email{dgisselq (at) opencores.org}
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\revision{Rev.~0.9}
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\revision{Rev.~0.91}
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\usepackage[dvips,ps2pdf,colorlinks=true,
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anchorcolor=black,pdfpagelabels,hypertexnames,
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pdfauthor={Dan Gisselquist},
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pdfsubject={Zip CPU}]{hyperref}
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pdfauthor={Dan Gisselquist},
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pdfsubject={Zip CPU},
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\begin{document}
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\begin{document}
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copy.
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copy.
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\end{license}
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\end{license}
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\begin{revisionhistory}
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\begin{revisionhistory}
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0.9 & 4/20/2016 & Gisselquist & Modified ISA: LDIHI replaced with MPY, MPYU and MPYS replaced with MPYUHI, and MPYSHI respectively. LOCK instruction now
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0.9 & 4/20/2016 & Gisselquist & Modified ISA: LDIHI replaced with MPY, MPYU and MPYS replaced with MPYUHI, and MPYSHI respectively. LOCK instruction now
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permits an intermediate ALU operation. \\\hline
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permits an intermediate ALU operation. \\\hline
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0.91& 7/16/2016 & Gisselquist & :escribed three more CC bits\\\hline
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0.8 & 1/28/2016 & Gisselquist & Reduced complexity early branching \\\hline
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0.8 & 1/28/2016 & Gisselquist & Reduced complexity early branching \\\hline
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0.7 & 12/22/2015 & Gisselquist & New Instruction Set Architecture \\\hline
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0.7 & 12/22/2015 & Gisselquist & New Instruction Set Architecture \\\hline
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0.6 & 11/17/2015 & Gisselquist & Added graphics to illustrate pipeline discussion.\\\hline
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0.6 & 11/17/2015 & Gisselquist & Added graphics to illustrate pipeline discussion.\\\hline
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0.5 & 9/29/2015 & Gisselquist & Added pipelined memory access discussion.\\\hline
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0.5 & 9/29/2015 & Gisselquist & Added pipelined memory access discussion.\\\hline
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0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline
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0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline
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The status register is special, and bears further mention. As shown in
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The status register is special, and bears further mention. As shown in
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Fig.~\ref{tbl:cc-register},
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Fig.~\ref{tbl:cc-register},
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\begin{table}\begin{center}
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\begin{table}\begin{center}
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\begin{bitlist}
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\begin{bitlist}
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31\ldots 13 & R/W & Reserved for future uses\\\hline
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31\ldots 23 & R & Reserved for future uses\\\hline
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22\ldots 15 & R/W & Reserved for future uses\\\hline
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14 & W & Clear I-Cache command\\\hline
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13 & R & VLIW instruction phase (1 for first half)\\\hline
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12 & R & (Reserved for) Floating Point Exception\\\hline
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12 & R & (Reserved for) Floating Point Exception\\\hline
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11 & R & Division by Zero Exception\\\hline
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11 & R & Division by Zero Exception\\\hline
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10 & R & Bus-Error Flag\\\hline
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10 & R & Bus-Error Flag\\\hline
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9 & R & Trap, or user interrupt, Flag. Cleared on return to userspace.\\\hline
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9 & R & Trap Flag (or user interrupt). Cleared on return to userspace.\\\hline
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8 & R & Illegal Instruction Flag\\\hline
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8 & R & Illegal Instruction Flag\\\hline
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7 & R/W & Break--Enable\\\hline
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7 & R/W & Break--Enable (sCC), or user break (uCC)\\\hline
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6 & R/W & Step\\\hline
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6 & R/W & Step\\\hline
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5 & R/W & Global Interrupt Enable (GIE)\\\hline
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5 & R/W & Global Interrupt Enable (GIE)\\\hline
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4 & R/W & Sleep. When GIE is also set, the CPU waits for an interrupt.\\\hline
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4 & R/W & Sleep. When GIE is also set, the CPU waits for an interrupt.\\\hline
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3 & R/W & Overflow\\\hline
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3 & R/W & Overflow\\\hline
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2 & R/W & Negative. The sign bit was set as a result of the last ALU instruction.\\\hline
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2 & R/W & Negative. The sign bit was set as a result of the last ALU instruction.\\\hline
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1 & R/W & Carry\\\hline
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1 & R/W & Carry\\\hline
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0 & R/W & Zero. The last ALU operation produced a zero.\\\hline
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0 & R/W & Zero. The last ALU operation produced a zero.\\\hline
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\end{bitlist}
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\end{bitlist}
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\caption{Condition Code Register Bit Assignment}\label{tbl:cc-register}
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\caption{Condition Code Register Bit Assignment}\label{tbl:cc-register}
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\end{center}\end{table}
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\end{center}\end{table}
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the lower 11~bits of the status register form
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the lower 15~bits of the status register form
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a set of CPU state and condition codes. Writes to other bits of this register
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a set of CPU state and condition codes. Writes to other bits of this register
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are preserved.
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are preserved.
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Of the condition codes, the bottom four bits are the current flags:
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Of the condition codes, the bottom four bits are the current flags:
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Zero (Z),
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Zero (Z),
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This functionality was added to enable a userspace debugger
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This functionality was added to enable a userspace debugger
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functionality on a user process, working through supervisor mode
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functionality on a user process, working through supervisor mode
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of course.
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of course.
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The eighth bit is a break enable bit. This controls whether a break
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The eighth bit is a break enable bit. When applied to the supervisor CC
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instruction in user mode will halt the processor for an external debugger
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register, this controls whether a break instruction in user mode will halt
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(break enabled), or whether the break instruction will simply send send the
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the processor for an external debugger (break enabled), or whether the break
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CPU into interrupt mode. Encountering a break in supervisor mode will
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instruction will simply send send the CPU into interrupt mode. Encountering
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halt the CPU independent of the break enable bit. This bit can only be set
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a break in supervisor mode will halt the CPU independent of the break enable
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within supervisor mode.
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bit. This bit can only be set within supervisor mode. However, when applied
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to the user CC register, from supervisor mode, this bit will indicate whether
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or not the reason the CPU entered supervisor mode was from a break instruction
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or not. This break reason bit is automatically cleared upon any transition to
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user mode, although it can also be cleared by the supervisor writing to the
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user CC register.
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% Should break enable be a supervisor mode bit, while the break enable bit
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% Should break enable be a supervisor mode bit, while the break enable bit
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% in user mode is a break has taken place bit?
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% in user mode is a break has taken place bit?
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%
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%
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The tenth bit is a trap bit. It is set whenever the user requests a soft
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The tenth bit is a trap bit. It is set whenever the user requests a soft
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interrupt, and cleared on any return to userspace command. This allows the
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interrupt, and cleared on any return to userspace command. This allows the
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supervisor, in supervisor mode, to determine whether it got to supervisor
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supervisor, in supervisor mode, to determine whether it got to supervisor
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mode from a trap or from an external interrupt or both.
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mode from a trap or from an external interrupt or both.
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The eleventh bit is a bus error flag. If the user program encountered a bus
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error, this bit will be set in the user CC register and the CPU will switch to
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supervisor mode. The bit may be cleared by the supervisor, otherwise it is
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automatically cleared upon any return to user mode. If the supervisor
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encounters a bus error, this bit will be set in the supervisor CC register
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and the CPU will halt. In that case, either a CPU reset or a write to the
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supervisor CC register will clear this register.
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The twelth bit is a division by zero exception flag. This operates in a fashion
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similar to the bus error flag. If the user attempts to use the divide
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instruction with a zero denominator, the system will switch to supervisor mode
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and set this bit in the user CC register. The bit is automatically cleared
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upon any return to user mode, although it can also be manually cleared by
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the supervisor. In a similar fashion, if the supervisor attempts to execute
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a divide by zero, the CPU will halt and set the zero exception flag in the
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supervisor's CC register. This will automatically be cleared upon any CPU
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reset, or it may be manually cleared by the external debugger writing to this
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register.
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The thirteenth bit will operate in a similar fashion to both the bus error
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and division by zero flags, only it will be set upon a (yet to be determined)
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floating point error.
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Finally, the fourteenth bit references a clear cache bit. The supervisor may
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write a one to this bit in order to clear the CPU instruction cache. The
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bit always reads as a zero.
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Some of the upper bits have been temporarily assigned to indicate CPU
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capabilities. This is not a permanent feature, as these upper bits officially
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remain reserved.
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\section{Instruction Format}
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\section{Instruction Format}
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All Zip CPU instructions fit in one of the formats shown in
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All Zip CPU instructions fit in one of the formats shown in
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Fig.~\ref{fig:iset-format}.
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Fig.~\ref{fig:iset-format}.
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\begin{figure}\begin{center}
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\begin{figure}\begin{center}
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\begin{bytefield}[endianness=big]{32}
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\begin{bytefield}[endianness=big]{32}
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15 & R/W & Set to `1' to trigger on an interrupt, or `0' to start immediately
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15 & R/W & Set to `1' to trigger on an interrupt, or `0' to start immediately
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upon receiving a valid key.\\\hline
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upon receiving a valid key.\\\hline
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14\ldots 10 & R/W & Select among one of 32~possible interrupt lines.\\\hline
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14\ldots 10 & R/W & Select among one of 32~possible interrupt lines.\\\hline
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9\ldots 0 & R/W & Intermediate transfer length minus one. Thus, to transfer
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9\ldots 0 & R/W & Intermediate transfer length minus one. Thus, to transfer
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one item at a time set this value to 0. To transfer 1024 at a time,
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one item at a time set this value to 0. To transfer 1024 at a time,
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set it to 1024.\\\hline
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set it to 1023.\\\hline
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\end{bitlist}
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\end{bitlist}
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\caption{DMA Control Register Bits}\label{tbl:dmacbits}
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\caption{DMA Control Register Bits}\label{tbl:dmacbits}
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\end{center}\end{table}
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\end{center}\end{table}
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This control register has been designed so that the common case of memory
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This control register has been designed so that the common case of memory
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access need only set the key and the transfer length. Hence, writing a
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access need only set the key and the transfer length. Hence, writing a
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might wish to write \hbox{32'h2fed8000}--this assumes, of course, that you
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might wish to write \hbox{32'h2fed8000}--this assumes, of course, that you
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have a serial port wired to the zero bit of this interrupt control. (The
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have a serial port wired to the zero bit of this interrupt control. (The
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DMA controller does not use the interrupt controller, and cannot clear
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DMA controller does not use the interrupt controller, and cannot clear
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interrupts.) As a third example, if you wished to write to an external
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interrupts.) As a third example, if you wished to write to an external
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FIFO anytime it was less than half full (had fewer than 512 items), and
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FIFO anytime it was less than half full (had fewer than 512 items), and
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interrupt line 2 indicated this condition, you might wish to issue a
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interrupt line 3 indicated this condition, you might wish to issue a
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\hbox{32'h1fed8dff} to this port.
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\hbox{32'h1fed8dff} to this port.
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\section{Debug Port Registers}
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\section{Debug Port Registers}
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Accessing the Zip System via the debug port isn't as straight forward as
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Accessing the Zip System via the debug port isn't as straight forward as
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accessing the system via the wishbone bus. The debug port itself has been
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accessing the system via the wishbone bus. The debug port itself has been
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