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[/] [zipcpu/] [trunk/] [doc/] [src/] [spec.tex] - Diff between revs 21 and 22
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| Rev 21 |
Rev 22 |
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{\tt o\_dbg\_ack} & {\tt ACK\_O} \\
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{\tt o\_dbg\_ack} & {\tt ACK\_O} \\
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{\tt o\_dbg\_stall} & {\tt STALL\_O} \\
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{\tt o\_dbg\_stall} & {\tt STALL\_O} \\
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{\tt o\_dbg\_data} & {\tt DAT\_O}
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{\tt o\_dbg\_data} & {\tt DAT\_O}
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\end{tabular}\\\hline
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\end{tabular}\\\hline
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\end{wishboneds}
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\end{wishboneds}
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\caption{Wishbone Datasheet}\label{tbl:wishbone-slave}
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\caption{Wishbone Datasheet for the Debug Interface}\label{tbl:wishbone-slave}
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\end{center}\end{table}
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\end{center}\end{table}
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and Tbl.~\ref{tbl:wishbone-master} respectively.
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and Tbl.~\ref{tbl:wishbone-master} respectively.
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\begin{table}[htbp]
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\begin{table}[htbp]
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\begin{center}
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\begin{center}
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\begin{wishboneds}
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\begin{wishboneds}
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{\tt i\_wb\_ack} & {\tt ACK\_I} \\
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{\tt i\_wb\_ack} & {\tt ACK\_I} \\
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{\tt i\_wb\_stall} & {\tt STALL\_I} \\
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{\tt i\_wb\_stall} & {\tt STALL\_I} \\
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{\tt i\_wb\_data} & {\tt DAT\_I}
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{\tt i\_wb\_data} & {\tt DAT\_I}
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\end{tabular}\\\hline
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\end{tabular}\\\hline
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\end{wishboneds}
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\end{wishboneds}
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\caption{Wishbone Datasheet}\label{tbl:wishbone-master}
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\caption{Wishbone Datasheet for the CPU as Master}\label{tbl:wishbone-master}
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\end{center}\end{table}
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\end{center}\end{table}
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I do not recommend that you connect these together through the interconnect.
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I do not recommend that you connect these together through the interconnect.
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The big thing to notice is that both the real time clock and the real time
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The big thing to notice is that both the real time clock and the real time
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date modules act as wishbone slaves, and that all accesses to the registers of
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date modules act as wishbone slaves, and that all accesses to the registers of
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