| Line 409... |
Line 409... |
The tenth bit is a trap bit. It is set whenever the user requests a soft
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The tenth bit is a trap bit. It is set whenever the user requests a soft
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interrupt, and cleared on any return to userspace command. This allows the
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interrupt, and cleared on any return to userspace command. This allows the
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supervisor, in supervisor mode, to determine whether it got to supervisor
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supervisor, in supervisor mode, to determine whether it got to supervisor
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mode from a trap or from an external interrupt or both.
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mode from a trap or from an external interrupt or both.
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|
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These status register bits are summarized in Tbl.~\ref{tbl:ccbits}.
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\begin{table}
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\begin{center}
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\begin{tabular}{l|l}
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Bit & Meaning \\\hline
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9 & Soft trap, set on a trap from user mode, cleared when returning to user mode\\\hline
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8 & (Reserved for) Floating point enable \\\hline
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7 & Halt on break, to support an external debugger \\\hline
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6 & Step, single step the CPU in user mode\\\hline
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5 & GIE, or Global Interrupt Enable \\\hline
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4 & Sleep \\\hline
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3 & V, or overflow bit.\\\hline
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2 & N, or negative bit.\\\hline
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1 & C, or carry bit.\\\hline
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0 & Z, or zero bit. \\\hline
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\end{tabular}
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\caption{Condition Code / Status Register Bits}\label{tbl:ccbits}
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\end{center}\end{table}
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\section{Conditional Instructions}
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\section{Conditional Instructions}
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Most, although not quite all, instructions may be conditionally executed. From
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Most, although not quite all, instructions may be conditionally executed. From
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the four condition code flags, eight conditions are defined. These are shown
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the four condition code flags, eight conditions are defined. These are shown
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in Tbl.~\ref{tbl:conditions}.
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in Tbl.~\ref{tbl:conditions}.
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\begin{table}
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\begin{table}
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| Line 830... |
Line 811... |
operations have consequences in that they might stall the bus if
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operations have consequences in that they might stall the bus if
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Rx isn't ready yet. For this reason, we have a dedicated NOOP
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Rx isn't ready yet. For this reason, we have a dedicated NOOP
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instruction. \\\hline
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instruction. \\\hline
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NOT Rx & XOR \$-1,Rx & \\\hline
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NOT Rx & XOR \$-1,Rx & \\\hline
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POP Rx
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POP Rx
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& \parbox[t]{1.5in}{LOD \$-1(SP),Rx \\ ADD \$1,SP}
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& \parbox[t]{1.5in}{LOD \$1(SP),Rx \\ ADD \$1,SP}
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& Note
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& Note
|
that for interrupt purposes, one can never depend upon the value at
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that for interrupt purposes, one can never depend upon the value at
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(SP). Hence you read from it, then increment it, lest having
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(SP). Hence you read from it, then increment it, lest having
|
incremented it first something then comes along and writes to that
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incremented it first something then comes along and writes to that
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value before you can read the result. \\\hline
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value before you can read the result. \\\hline
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| Line 909... |
Line 890... |
a TRAP bit within the CC register. Therefore, upon entering the
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a TRAP bit within the CC register. Therefore, upon entering the
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supervisor state, the CPU only need check this bit to know that it
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supervisor state, the CPU only need check this bit to know that it
|
got there via a TRAP. The trap could be made conditional by making
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got there via a TRAP. The trap could be made conditional by making
|
the LDI and the AND conditional. In that case, the assembler would
|
the LDI and the AND conditional. In that case, the assembler would
|
quietly turn the LDI instruction into an LDILO and LDIHI pair,
|
quietly turn the LDI instruction into an LDILO and LDIHI pair,
|
but the effectt would be the same. \\\hline
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but the effect would be the same. \\\hline
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\end{tabular}
|
\end{tabular}
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\caption{Derived Instructions, continued}\label{tbl:derived-3}
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\caption{Derived Instructions, continued}\label{tbl:derived-3}
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\end{center}\end{table}
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\end{center}\end{table}
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\begin{table}\begin{center}
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\begin{table}\begin{center}
|
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
|
\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline
|
