Subversion Repositories zipcpu

\documentclass{gqtekspec}

\documentclass{gqtekspec}

\project{Zip CPU}

\project{Zip CPU}

\title{Specification}

\title{Specification}

\author{Dan Gisselquist, Ph.D.}

\author{Dan Gisselquist, Ph.D.}

\email{dgisselq (at) opencores.org}

\email{dgisselq (at) opencores.org}

\definecolor{webred}{rgb}{0.2,0,0}

\definecolor{webred}{rgb}{0.2,0,0}

\definecolor{webgreen}{rgb}{0,0.2,0}

\definecolor{webgreen}{rgb}{0,0.2,0}

\usepackage[dvips,ps2pdf,colorlinks=true,

\usepackage[dvips,ps2pdf,colorlinks=true,

        anchorcolor=black,pagecolor=webgreen,pdfpagelabels,hypertexnames,

        anchorcolor=black,pagecolor=webgreen,pdfpagelabels,hypertexnames,

        pdfauthor={Dan Gisselquist},

        pdfauthor={Dan Gisselquist},

You should have received a copy of the GNU General Public License along

You should have received a copy of the GNU General Public License along

with this program.  If not, see \hbox{<http://www.gnu.org/licenses/>} for a

with this program.  If not, see \hbox{<http://www.gnu.org/licenses/>} for a

copy.

copy.

\end{license}

\end{license}

\begin{revisionhistory}

\begin{revisionhistory}

0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline

0.4 & 9/19/2015 & Gisselquist & Added DMA controller, improved stall information, and self--assessment info.\\\hline

0.3 & 8/22/2015 & Gisselquist & First completed draft\\\hline

0.3 & 8/22/2015 & Gisselquist & First completed draft\\\hline

0.2 & 8/19/2015 & Gisselquist & Still Draft, more complete \\\hline

0.2 & 8/19/2015 & Gisselquist & Still Draft, more complete \\\hline

0.1 & 8/17/2015 & Gisselquist & Incomplete First Draft \\\hline

0.1 & 8/17/2015 & Gisselquist & Incomplete First Draft \\\hline

\end{revisionhistory}

\end{revisionhistory}

The tenth bit is a trap bit.  It is set whenever the user requests a soft

The tenth bit is a trap bit.  It is set whenever the user requests a soft

interrupt, and cleared on any return to userspace command.  This allows the

interrupt, and cleared on any return to userspace command.  This allows the

supervisor, in supervisor mode, to determine whether it got to supervisor

supervisor, in supervisor mode, to determine whether it got to supervisor

mode from a trap or from an external interrupt or both.

mode from a trap or from an external interrupt or both.

\section{Conditional Instructions}

\section{Conditional Instructions}

Most, although not quite all, instructions may be conditionally executed.  From

Most, although not quite all, instructions may be conditionally executed.  From

the four condition code flags, eight conditions are defined.  These are shown

the four condition code flags, eight conditions are defined.  These are shown

in Tbl.~\ref{tbl:conditions}.

in Tbl.~\ref{tbl:conditions}.

\begin{table}

\begin{table}

\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|c|}\hline

\begin{tabular}{|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|l|c|}\hline

\rowcolor[gray]{0.85}

\rowcolor[gray]{0.85}

Op Code & \multicolumn{8}{c|}{31\ldots24} & \multicolumn{8}{c|}{23\ldots 16}

Op Code & \multicolumn{8}{c|}{31\ldots24} & \multicolumn{8}{c|}{23\ldots 16}

        & \multicolumn{8}{c|}{15\ldots 8} & \multicolumn{8}{c|}{7\ldots 0}

        & \multicolumn{8}{c|}{15\ldots 8} & \multicolumn{8}{c|}{7\ldots 0}

        & Sets CC? \\\hline\hline

        & Sets CC? \\\hline\hline

                & \multicolumn{4}{l|}{D. Reg}

                & \multicolumn{4}{l|}{D. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{21}{l|}{Operand B}

                & \multicolumn{21}{l|}{Operand B}

                & Yes \\\hline

                & Yes \\\hline

                & \multicolumn{4}{l|}{D. Reg}

                & \multicolumn{4}{l|}{D. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{21}{l|}{Operand B}

                & \multicolumn{21}{l|}{Operand B}

        & Yes \\\hline

        & Yes \\\hline

                & \multicolumn{4}{l|}{D. Reg}

                & \multicolumn{4}{l|}{D. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{3}{l|}{Cond.}

                & A-Usr

                & A-Usr

                & \multicolumn{4}{l|}{B-Reg}

                & \multicolumn{4}{l|}{B-Reg}

                & B-Usr

                & B-Usr

                & \multicolumn{15}{l|}{15'bit signed offset}

                & \multicolumn{15}{l|}{15'bit signed offset}

                & \\\hline

                & \\\hline

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{24}{l|}{24'bit Signed Immediate}

                & \multicolumn{24}{l|}{24'bit Signed Immediate}

                & \\\hline

                & \\\hline

                & \multicolumn{4}{l|}{4'he}

                & \multicolumn{4}{l|}{4'he}

                & \multicolumn{24}{l|}{24'h00}

                & \multicolumn{24}{l|}{24'h00}

                & \\\hline

                & \\\hline

                & \multicolumn{4}{l|}{4'he}

                & \multicolumn{4}{l|}{4'he}

                & \multicolumn{24}{l|}{24'h01}

                & \multicolumn{24}{l|}{24'h01}

                & \\\hline

                & \\\hline

{\em Reserved} & \multicolumn{4}{l|}{4'h4}

{\em Reserved} & \multicolumn{4}{l|}{4'h4}

                & \multicolumn{4}{l|}{4'he}

                & \multicolumn{4}{l|}{4'he}

                & \multicolumn{24}{l|}{24'bits, but not 0 or 1.}

                & \multicolumn{24}{l|}{24'bits, but not 0 or 1.}

                & \\\hline

                & \\\hline

                & \multicolumn{4}{l|}{4'hf}

                & \multicolumn{4}{l|}{4'hf}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{3}{l|}{Cond.}

                & 1'b1

                & 1'b1

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{16}{l|}{16-bit Immediate}

                & \multicolumn{16}{l|}{16-bit Immediate}

                & \\\hline

                & \\\hline

                & \multicolumn{4}{l|}{4'hf}

                & \multicolumn{4}{l|}{4'hf}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{3}{l|}{Cond.}

                & 1'b0

                & 1'b0

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{16}{l|}{16-bit Immediate}

                & \multicolumn{16}{l|}{16-bit Immediate}

                & \\\hline

                & \\\hline

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{3}{l|}{Cond.}

                & 1'b0 & \multicolumn{4}{l|}{Reg}

                & 1'b0 & \multicolumn{4}{l|}{Reg}

                & \multicolumn{16}{l|}{16-bit Offset}

                & \multicolumn{16}{l|}{16-bit Offset}

                & Yes \\\hline

                & Yes \\\hline

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{3}{l|}{Cond.}

                & 1'b0 & \multicolumn{4}{l|}{4'hf}

                & 1'b0 & \multicolumn{4}{l|}{4'hf}

                & \multicolumn{16}{l|}{16-bit Offset}

                & \multicolumn{16}{l|}{16-bit Offset}

                & Yes \\\hline

                & Yes \\\hline

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{3}{l|}{Cond.}

                & 1'b1 & \multicolumn{4}{l|}{Reg}

                & 1'b1 & \multicolumn{4}{l|}{Reg}

                & \multicolumn{16}{l|}{16-bit Offset}

                & \multicolumn{16}{l|}{16-bit Offset}

                & Yes \\\hline

                & Yes \\\hline

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{3}{l|}{Cond.}

                & 1'b1 & \multicolumn{4}{l|}{4'hf}

                & 1'b1 & \multicolumn{4}{l|}{4'hf}

                & \multicolumn{16}{l|}{16-bit Offset}

                & \multicolumn{16}{l|}{16-bit Offset}

                & Yes \\\hline

                & Yes \\\hline

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{21}{l|}{Operand B, truncated to low order 5 bits}

                & \multicolumn{21}{l|}{Operand B, truncated to low order 5 bits}

                & \\\hline

                & \\\hline

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{4}{l|}{R. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{21}{l|}{Operand B address}

                & \multicolumn{21}{l|}{Operand B address}

                & \\\hline

                & \\\hline

                & \multicolumn{4}{l|}{D. Reg}

                & \multicolumn{4}{l|}{D. Reg}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{3}{l|}{Cond.}

                & \multicolumn{21}{l|}{Operand B address}

                & \multicolumn{21}{l|}{Operand B address}

                & \\\hline

                & \\\hline

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B}

        &       \multicolumn{21}{l|}{Operand B}

        & Yes \\\hline

        & Yes \\\hline

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B}

        &       \multicolumn{21}{l|}{Operand B}

        & Yes \\\hline

        & Yes \\\hline

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B}

        &       \multicolumn{21}{l|}{Operand B}

        & Yes \\\hline

        & Yes \\\hline

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B}

        &       \multicolumn{21}{l|}{Operand B}

        & Yes \\\hline

        & Yes \\\hline

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B}

        &       \multicolumn{21}{l|}{Operand B}

        & Yes \\\hline

        & Yes \\\hline

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}

        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}

        & Yes \\\hline

        & Yes \\\hline

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}

        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}

        & Yes \\\hline

        & Yes \\\hline

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{4}{l|}{R. Reg}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{3}{l|}{Cond.}

        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}

        &       \multicolumn{21}{l|}{Operand B, imm. truncated to 6 bits}

        & Yes \\\hline

        & Yes \\\hline

\end{tabular}

\end{tabular}

the Zip CPU.  Many of these instructions will have assembly equivalents,

the Zip CPU.  Many of these instructions will have assembly equivalents,

such as the branch instructions, to facilitate working with the CPU.

such as the branch instructions, to facilitate working with the CPU.

\begin{table}\begin{center}

\begin{table}\begin{center}

\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline

\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline

Mapped & Actual  & Notes \\\hline

Mapped & Actual  & Notes \\\hline

        & Absolute value, depends upon derived NEG.\\\hline

        & Absolute value, depends upon derived NEG.\\\hline

        & Add with carry \\\hline

        & Add with carry \\\hline

        & Branch or jump on condition.  Works for 15--bit

        & Branch or jump on condition.  Works for 15--bit

                signed address offsets.\\\hline

                signed address offsets.\\\hline

        & Branch/jump on condition.  Works for

        & Branch/jump on condition.  Works for

        23 bit address offsets, but costs a register, an extra instruction,

        23 bit address offsets, but costs a register, an extra instruction,

        and sets the flags. \\\hline

        and sets the flags. \\\hline

        & Example of a branch on an unsupported

        & Example of a branch on an unsupported

                condition, in this case a branch on not carry \\\hline

                condition, in this case a branch on not carry \\\hline

        & Clear Rx, and flags, if the Z-bit is not set \\\hline

        & Clear Rx, and flags, if the Z-bit is not set \\\hline

        & Clears Rx, leaves flags untouched.  This instruction cannot be

        & Clears Rx, leaves flags untouched.  This instruction cannot be

                conditional. \\\hline

                conditional. \\\hline

        & Exchanges the top and bottom 16'bit words of Rx \\\hline

        & Exchanges the top and bottom 16'bit words of Rx \\\hline

        & \\\hline

        & \\\hline

        MOV \$3+PC,R0 \\

        MOV \$3+PC,R0 \\

        STO R0,1(SP) \\

        STO R0,1(SP) \\

        MOV \$Addr+PC,PC \\

        MOV \$Addr+PC,PC \\

        ADD \$1,SP}

        ADD \$1,SP}

        & Jump to Subroutine. Note the required cleanup instruction after

        & Jump to Subroutine. Note the required cleanup instruction after

        returning.  This could easily be turned into a three instruction

        returning.  This could easily be turned into a three instruction

        operand, removing the preliminary stack instruction before and

        operand, removing the preliminary stack instruction before and

        the cleanup after, by adjusting how any stack frame was built for

        the cleanup after, by adjusting how any stack frame was built for

        this routine to include space at the top of the stack for the PC.

        this routine to include space at the top of the stack for the PC.

        \\\hline

        \\\hline

        &This is the high speed

        &This is the high speed

        version of a subroutine call, necessitating a register to hold the

        version of a subroutine call, necessitating a register to hold the

        last PC address.  In its favor, this method doesn't suffer the

        last PC address.  In its favor, this method doesn't suffer the

        mandatory memory access of the other approach. \\\hline

        mandatory memory access of the other approach. \\\hline

        & Sadly, there's not enough instruction

        & Sadly, there's not enough instruction

                space to load a complete immediate value into any register.

                space to load a complete immediate value into any register.

                Therefore, fully loading any register takes two cycles.

                Therefore, fully loading any register takes two cycles.

                The LDIHI (load immediate high) and LDILO (load immediate low)

                The LDIHI (load immediate high) and LDILO (load immediate low)

                instructions have been created to facilitate this. \\\hline

                instructions have been created to facilitate this. \\\hline

\caption{Derived Instructions}\label{tbl:derived-1}

\caption{Derived Instructions}\label{tbl:derived-1}

\end{center}\end{table}

\end{center}\end{table}

\begin{table}\begin{center}

\begin{table}\begin{center}

\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline

\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline

Mapped & Actual  & Notes \\\hline

Mapped & Actual  & Notes \\\hline

        LDI     \$addr,Ra \\

        LDI     \$addr,Ra \\

        LDI     \$addr,Rb \\

        LDI     \$addr,Rb \\

        LSR     \$2,Ra \\

        LSR     \$2,Ra \\

        AND     \$3,Rb \\

        AND     \$3,Rb \\

        LOD     (Ra),Rx \\

        LOD     (Ra),Rx \\

        all other addresses in this document are 32-bit wordlength addresses.

        all other addresses in this document are 32-bit wordlength addresses.

        For this reason,

        For this reason,

        we needed to drop the bottom two bits.  This also limits the address

        we needed to drop the bottom two bits.  This also limits the address

        space of character accesses using this method from 16 MB down to 4MB.}

        space of character accesses using this method from 16 MB down to 4MB.}

                \\\hline

                \\\hline

        LSL \$1,Rx \\

        LSL \$1,Rx \\

        OR.C \$1,Ry}

        OR.C \$1,Ry}

        & Logical shift left with carry.  Note that the

        & Logical shift left with carry.  Note that the

        instruction order is now backwards, to keep the conditions valid.

        instruction order is now backwards, to keep the conditions valid.

        That is, LSL sets the carry flag, so if we did this the other way

        That is, LSL sets the carry flag, so if we did this the other way

        with Rx before Ry, then the condition flag wouldn't have been right

        with Rx before Ry, then the condition flag wouldn't have been right

        for an OR correction at the end. \\\hline

        for an OR correction at the end. \\\hline

        LSR \$1,Ry \\

        LSR \$1,Ry \\

        LDIHI.C \$8000h,Rz \\

        LDIHI.C \$8000h,Rz \\

        LSR \$1,Rx \\

        LSR \$1,Rx \\

        OR Rz,Rx}

        OR Rz,Rx}

        & Logical shift right with carry \\\hline

        & Logical shift right with carry \\\hline

        operations that do nothing, such as MOV Rx,Rx, or OR \$0,Rx, these

        operations that do nothing, such as MOV Rx,Rx, or OR \$0,Rx, these

        operations have consequences in that they might stall the bus if

        operations have consequences in that they might stall the bus if

        Rx isn't ready yet.  For this reason, we have a dedicated NOOP

        Rx isn't ready yet.  For this reason, we have a dedicated NOOP

        instruction. \\\hline

        instruction. \\\hline

        & Note

        & Note

        that for interrupt purposes, one can never depend upon the value at

        that for interrupt purposes, one can never depend upon the value at

        (SP).  Hence you read from it, then increment it, lest having

        (SP).  Hence you read from it, then increment it, lest having

        incremented it first something then comes along and writes to that

        incremented it first something then comes along and writes to that

        value before you can read the result. \\\hline

        value before you can read the result. \\\hline

\end{tabular}

\end{tabular}

\caption{Derived Instructions, continued}\label{tbl:derived-2}

\caption{Derived Instructions, continued}\label{tbl:derived-2}

\end{center}\end{table}

\end{center}\end{table}

\begin{table}\begin{center}

\begin{table}\begin{center}

\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline

\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline

        & \parbox[t]{1.5in}{SUB \$1,SP \\

        & \parbox[t]{1.5in}{SUB \$1,SP \\

        STO Rx,\$1(SP)}

        STO Rx,\$1(SP)}

        STO Rx,\$n(SP)

        STO Rx,\$n(SP)

        \ldots \\

        \ldots \\

        STO Ry,\$1(SP)}

        STO Ry,\$1(SP)}

        & Multiple pushes at once only need the single subtract from the

        & Multiple pushes at once only need the single subtract from the

        stack pointer.  This derived instruction is analogous to a similar one

        stack pointer.  This derived instruction is analogous to a similar one

        on the Motoroloa 68k architecture, although the Zip Assembler

        on the Motoroloa 68k architecture, although the Zip Assembler

        in R12.

        in R12.

        Another opportunity might be to jump to the reset address from within

        Another opportunity might be to jump to the reset address from within

        & Note that this depends upon the calling context to clean up the

        & Note that this depends upon the calling context to clean up the

        stack, as outlined for the JSR instruction.  \\\hline

        stack, as outlined for the JSR instruction.  \\\hline

        & This is the high(er) speed version, that doesn't touch the stack.

        & This is the high(er) speed version, that doesn't touch the stack.

        As such, it doesn't suffer a stall on memory read/write to the stack.

        As such, it doesn't suffer a stall on memory read/write to the stack.

        \\\hline

        \\\hline

        & Step a Galois implementation of a Linear Feedback Shift Register, Rr,

        & Step a Galois implementation of a Linear Feedback Shift Register, Rr,

                using taps Rt \\\hline

                using taps Rt \\\hline

        LDI \$addr,Ra \\

        LDI \$addr,Ra \\

        LDI \$addr,Rb \\

        LDI \$addr,Rb \\

        LSR \$2,Ra \\

        LSR \$2,Ra \\

        AND \$3,Rb \\

        AND \$3,Rb \\

        SUB \$32,Rb \\

        SUB \$32,Rb \\

        LOD (Ra),Ry \\

        LOD (Ra),Ry \\

        AND \$0ffh,Rx \\

        AND \$0ffh,Rx \\

        ROL Rb,Rx \\

        ROL Rb,Rx \\

        OR Rx,Ry \\

        OR Rx,Ry \\

        STO Ry,(Ra) }

        STO Ry,(Ra) }

        & \parbox[t]{3in}{This CPU and it's bus are {\em not} optimized

        & \parbox[t]{3in}{This CPU and it's bus are {\em not} optimized

        for byte-wise operations.

        for byte-wise operations.

        byte-wise address, whereas in all of our other examples it is a

        byte-wise address, whereas in all of our other examples it is a

        32-bit word address. This also limits the address space

        32-bit word address. This also limits the address space

        of character accesses from 16 MB down to 4MB.F

        of character accesses from 16 MB down to 4MB.F

        Further, this instruction implies a byte ordering,

        Further, this instruction implies a byte ordering,

        such as big or little endian.} \\\hline

        such as big or little endian.} \\\hline

        XOR Ry,Rx \\

        XOR Ry,Rx \\

        XOR Rx,Ry \\

        XOR Rx,Ry \\

        XOR Ry,Rx}

        XOR Ry,Rx}

        & While no extra registers are needed, this example

        & While no extra registers are needed, this example

        does take 3-clocks. \\\hline

        does take 3-clocks. \\\hline

        & This works because whenever a user lowers the \$GIE flag, it sets

        & This works because whenever a user lowers the \$GIE flag, it sets

        a TRAP bit within the CC register.  Therefore, upon entering the

        a TRAP bit within the CC register.  Therefore, upon entering the

        supervisor state, the CPU only need check this bit to know that it

        supervisor state, the CPU only need check this bit to know that it

        got there via a TRAP.  The trap could be made conditional by making

        got there via a TRAP.  The trap could be made conditional by making

        the LDI and the AND conditional.  In that case, the assembler would

        the LDI and the AND conditional.  In that case, the assembler would

\end{tabular}

\end{tabular}

\caption{Derived Instructions, continued}\label{tbl:derived-3}

\caption{Derived Instructions, continued}\label{tbl:derived-3}

\end{center}\end{table}

\end{center}\end{table}

\begin{table}\begin{center}

\begin{table}\begin{center}

\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline

\begin{tabular}{p{1.4in}p{1.5in}p{3in}}\\\hline

        & Set the condition codes based upon Rx.  Could also do a CMP \$0,Rx,

        & Set the condition codes based upon Rx.  Could also do a CMP \$0,Rx,

        ADD \$0,Rx, SUB \$0,Rx, etc, AND \$-1,Rx, etc.  The TST and CMP

        ADD \$0,Rx, SUB \$0,Rx, etc, AND \$-1,Rx, etc.  The TST and CMP

        approaches won't stall future pipeline stages looking for the value

        approaches won't stall future pipeline stages looking for the value

        of Rx. \\\hline

        of Rx. \\\hline

\end{tabular}

\end{tabular}

\caption{Derived Instructions, continued}\label{tbl:derived-4}

\caption{Derived Instructions, continued}\label{tbl:derived-4}

\end{center}\end{table}

\end{center}\end{table}

\section{Pipeline Stages}

\section{Pipeline Stages}

As mentioned in the introduction, and highlighted in Fig.~\ref{fig:cpu},

As mentioned in the introduction, and highlighted in Fig.~\ref{fig:cpu},

In this case, the LOD instruction cannot start until the STO is finished.

In this case, the LOD instruction cannot start until the STO is finished.

With proper scheduling, it is possible to do something in the ALU while the

With proper scheduling, it is possible to do something in the ALU while the

memory unit is busy with the STO instruction, but otherwise this pipeline will

memory unit is busy with the STO instruction, but otherwise this pipeline will

stall waiting for it to complete.

stall waiting for it to complete.

\item When waiting for a conditional memory read operation to complete

\item When waiting for a conditional memory read operation to complete

\begin{enumerate}

\begin{enumerate}

\item\ {\tt LOD.Z address,RA}

\item\ {\tt LOD.Z address,RA}

\item\ {\em (multiple stalls, bus dependent, 7 clocks best)}

\item\ {\em (multiple stalls, bus dependent, 7 clocks best)}

restart its transfer by writing the contents of its internal buffer and then

restart its transfer by writing the contents of its internal buffer and then

re-entering its read cycle again.

re-entering its read cycle again.

When coupled with a peripheral, the DMA controller can be configured to start

When coupled with a peripheral, the DMA controller can be configured to start

a memory copy on an interrupt line going high.  Further, the controller can be

a memory copy on an interrupt line going high.  Further, the controller can be

the address at each clock.  The DMA completes once the total number of items

the address at each clock.  The DMA completes once the total number of items

specified (not the transfer length) have been transferred.

specified (not the transfer length) have been transferred.

In each case, once the transfer is complete and the DMA unit returns to

In each case, once the transfer is complete and the DMA unit returns to

idle, the DMA will issue an interrupt.

idle, the DMA will issue an interrupt.

        onto the user stack and then copying the resulting stack address

        onto the user stack and then copying the resulting stack address

        into the tasks task structure, as shown in Tbl.~\ref{tbl:context-out}.

        into the tasks task structure, as shown in Tbl.~\ref{tbl:context-out}.

\begin{table}\begin{center}

\begin{table}\begin{center}

\begin{tabular}{ll}

\begin{tabular}{ll}

{\tt swap\_out:} \\

{\tt swap\_out:} \\

&       {\em ; We can skip storing the stack, uSP, since it'll be stored}\\

&       {\em ; We can skip storing the stack, uSP, since it'll be stored}\\

&       {\em ; elsewhere (in the task structure) }\\

&       {\em ; elsewhere (in the task structure) }\\

\end{tabular}

\end{tabular}

\caption{Example Storing User Task Context}\label{tbl:context-out}

\caption{Example Storing User Task Context}\label{tbl:context-out}

\end{center}\end{table}

\end{center}\end{table}

For the sake of discussion, we assume the supervisor maintains a

For the sake of discussion, we assume the supervisor maintains a

pointer to the current task's structure in supervisor register

pointer to the current task's structure in supervisor register

        back off of the stack to run this task.  An example of this is

        back off of the stack to run this task.  An example of this is

        shown in Tbl.~\ref{tbl:context-in},

        shown in Tbl.~\ref{tbl:context-in},

\begin{table}\begin{center}

\begin{table}\begin{center}

\begin{tabular}{ll}

\begin{tabular}{ll}

{\tt swap\_in:} \\

{\tt swap\_in:} \\

&       {\tt MOV 15(R1),uSP} \\

&       {\tt MOV 15(R1),uSP} \\

&       {\tt MOV R0,uR0} \\

&       {\tt MOV R0,uR0} \\

&       {\tt BRA return\_to\_user} \\

&       {\tt BRA return\_to\_user} \\

\end{tabular}

\end{tabular}

\caption{Example Restoring User Task Context}\label{tbl:context-in}

\caption{Example Restoring User Task Context}\label{tbl:context-in}

\end{center}\end{table}

\end{center}\end{table}

        assuming as before that the task

        assuming as before that the task

The bit allocation of the control register is shown in Tbl.~\ref{tbl:dmacbits}.

The bit allocation of the control register is shown in Tbl.~\ref{tbl:dmacbits}.

\begin{table}\begin{center}

\begin{table}\begin{center}

\begin{bitlist}

\begin{bitlist}

31 & R & DMA Active\\\hline

31 & R & DMA Active\\\hline

29 & R/W & Set to '1' to prevent the controller from incrementing the source address, '0' for normal memory copy. \\\hline

29 & R/W & Set to '1' to prevent the controller from incrementing the source address, '0' for normal memory copy. \\\hline

        destination address, '0' for normal memory copy. \\\hline

        destination address, '0' for normal memory copy. \\\hline

27 \ldots 16 & W & The DMA Key.  Write a 12'hfed to these bits to start the

27 \ldots 16 & W & The DMA Key.  Write a 12'hfed to these bits to start the

        activate any DMA transfer.  \\\hline

        activate any DMA transfer.  \\\hline

27 & R & Always reads '0', to force the deliberate writing of the key. \\\hline

27 & R & Always reads '0', to force the deliberate writing of the key. \\\hline

26 \ldots 16 & R & Indicates the number of items in the transfer buffer that

26 \ldots 16 & R & Indicates the number of items in the transfer buffer that

uSP & 29 & 32 & R/W & User Stack Pointer\\\hline

uSP & 29 & 32 & R/W & User Stack Pointer\\\hline

uCC & 30 & 32 & R/W & User Condition Code Register \\\hline

uCC & 30 & 32 & R/W & User Condition Code Register \\\hline

uPC & 31 & 32 & R/W & User Program Counter\\\hline

uPC & 31 & 32 & R/W & User Program Counter\\\hline

PIC & 32 & 32 & R/W & Primary Interrupt Controller \\\hline

PIC & 32 & 32 & R/W & Primary Interrupt Controller \\\hline

WDT & 33 & 32 & R/W & Watchdog Timer\\\hline

WDT & 33 & 32 & R/W & Watchdog Timer\\\hline

CTRIC & 35 & 32 & R/W & Secondary Interrupt Controller\\\hline

CTRIC & 35 & 32 & R/W & Secondary Interrupt Controller\\\hline

TMRA & 36 & 32 & R/W & Timer A\\\hline

TMRA & 36 & 32 & R/W & Timer A\\\hline

TMRB & 37 & 32 & R/W & Timer B\\\hline

TMRB & 37 & 32 & R/W & Timer B\\\hline

TMRC & 38 & 32 & R/W & Timer C\\\hline

TMRC & 38 & 32 & R/W & Timer C\\\hline

JIFF & 39 & 32 & R/W & Jiffies peripheral\\\hline

JIFF & 39 & 32 & R/W & Jiffies peripheral\\\hline

MICNT & 43 & 32 & R/W & Master instruction counter\\\hline

MICNT & 43 & 32 & R/W & Master instruction counter\\\hline

UTASK & 44 & 32 & R/W & User task clock counter\\\hline

UTASK & 44 & 32 & R/W & User task clock counter\\\hline

UMSTL & 45 & 32 & R/W & User memory stall counter\\\hline

UMSTL & 45 & 32 & R/W & User memory stall counter\\\hline

UPSTL & 46 & 32 & R/W & User Pre-Fetch Stall counter\\\hline

UPSTL & 46 & 32 & R/W & User Pre-Fetch Stall counter\\\hline

UICNT & 47 & 32 & R/W & User instruction counter\\\hline

UICNT & 47 & 32 & R/W & User instruction counter\\\hline

\end{reglist}

\end{reglist}

\caption{Debug Register Addresses}\label{tbl:dbgaddrs}

\caption{Debug Register Addresses}\label{tbl:dbgaddrs}

\end{center}\end{table}

\end{center}\end{table}

Primarily, these ``registers'' include access to the entire CPU register

Primarily, these ``registers'' include access to the entire CPU register

set, as well as the internal peripherals.  To read one of these registers

set, as well as the internal peripherals.  To read one of these registers

        (yet) support a compiler. The standard C library is an even longer

        (yet) support a compiler. The standard C library is an even longer

        shot. My dream of having binutils and gcc support has not been

        shot. My dream of having binutils and gcc support has not been

        realized and at this rate may not be realized. (I've been intimidated

        realized and at this rate may not be realized. (I've been intimidated

        by the challenge everytime I've looked through those codes.)

        by the challenge everytime I've looked through those codes.)

\item While the Wishbone Bus (B4) supports a pipelined mode with single cycle

\item While the Wishbone Bus (B4) supports a pipelined mode with single cycle

        execution, the Zip CPU is unable to exploit this parallelism. Instead,

        execution, the Zip CPU is unable to exploit this parallelism. Instead,

        apart from the DMA and the pipelined prefetch, all loads and stores

        apart from the DMA and the pipelined prefetch, all loads and stores

        are single wishbone bus operations requiring a minimum of 3 clocks.

        are single wishbone bus operations requiring a minimum of 3 clocks.

        (In practice, this has turned into 7-clocks.)

        (In practice, this has turned into 7-clocks.)

\item There is no control over whether or not an instruction sets the

\item There is no control over whether or not an instruction sets the

        condition codes--certain instructions always set the condition codes,

        condition codes--certain instructions always set the condition codes,

        other instructions never set them. This effectively limits conditional

        other instructions never set them. This effectively limits conditional

        instructions to a single instruction only (with two or more

        instructions to a single instruction only (with two or more

        instructions as an exception), as the first instruction that sets

        instructions as an exception), as the first instruction that sets

        the process accounting registers are anything but light weight, why

        the process accounting registers are anything but light weight, why

        keep them?  Why not instead make some compile flags that just turn them

        keep them?  Why not instead make some compile flags that just turn them

        off, keeping the CPU lightweight?  The same holds for the prefetch

        off, keeping the CPU lightweight?  The same holds for the prefetch

        cache.

        cache.

\iffalse

\iffalse

\item {\bf Adjust the Zip CPU so that conditional instructions do not set

\item {\bf Adjust the Zip CPU so that conditional instructions do not set

        flags}, although they may explicitly set condition codes if writing

        flags}, although they may explicitly set condition codes if writing

        to the CC register.

        to the CC register.

        This is a simple change to the core, and may show up in new releases.

        This is a simple change to the core, and may show up in new releases.

        % Fixed, 20150918

        % Fixed, 20150918

\item Add in an {\bf unpredictable branch delay slot}, so that on any branch

\item Add in an {\bf unpredictable branch delay slot}, so that on any branch

        the delay slot may or may not be executed before the branch.

        the delay slot may or may not be executed before the branch.

        Instructions that do not depend upon the branch, and that should be

        Instructions that do not depend upon the branch, and that should be

        executed were the branch not taken, could be placed into the delay

        executed were the branch not taken, could be placed into the delay

        slot. Thus, if the branch isn't taken, we wouldn't suffer the stall,

        slot. Thus, if the branch isn't taken, we wouldn't suffer the stall,

        for one cycle before starting again, these extra cycles add up.

        for one cycle before starting again, these extra cycles add up.

        It should be possible to tell the prefetch stage to give up the bus

        It should be possible to tell the prefetch stage to give up the bus

        as soon as the decoder knows the instruction will need the bus.

        as soon as the decoder knows the instruction will need the bus.

        Indeed, if done in the decode stage, this might drop the seven cycle

        Indeed, if done in the decode stage, this might drop the seven cycle

        access down by two cycles.

        access down by two cycles.

        % FIXED: 20150918

        % FIXED: 20150918

\item {\bf Very Long Instruction Word (VLIW).}  Now, to speed up operation, I

\item {\bf Very Long Instruction Word (VLIW).}  Now, to speed up operation, I

        propose that the Zip CPU instruction set be modified towards a Very

        propose that the Zip CPU instruction set be modified towards a Very

        Long Instruction Word (VLIW) implementation. In this implementation,

        Long Instruction Word (VLIW) implementation. In this implementation,

        an instruction word may contain either one or two separate

        an instruction word may contain either one or two separate

        instructions. The first instruction would take up the high order bits,

        instructions. The first instruction would take up the high order bits,