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https://opencores.org/ocsvn/zipcpu/zipcpu/trunk
[/] [zipcpu/] [trunk/] [rtl/] [aux/] [busdelay.v] - Diff between revs 2 and 15
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Rev 15 |
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Line 85... |
always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_ack <= (i_dly_ack)&&(o_dly_cyc)&&(i_wb_cyc);
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o_wb_ack <= (i_dly_ack)&&(o_dly_cyc)&&(i_wb_cyc);
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_wb_data <= i_dly_data;
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o_wb_data <= i_dly_data;
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// Our only non-delayed line, yet still really delayed.
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// Our only non-delayed line, yet still really delayed. Perhaps
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assign o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall));
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// there's a way to register this?
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// o_wb_stall <= (i_wb_cyc)&&(i_wb_stb) ... or some such?
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assign o_wb_stall = ((i_wb_cyc)&&(o_dly_cyc)&&(i_dly_stall)&&(~o_dly_stb));
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endmodule
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endmodule
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