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[/] [zipcpu/] [trunk/] [rtl/] [aux/] [wbarbiter.v] - Diff between revs 69 and 180
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| Rev 69 |
Rev 180 |
| Line 112... |
Line 112... |
// first clock of the bus cycle
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// first clock of the bus cycle
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reg r_a_owner, r_b_owner;
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reg r_a_owner, r_b_owner;
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wire w_a_owner, w_b_owner;
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wire w_a_owner, w_b_owner;
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`ifdef WBA_ALTERNATING
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`ifdef WBA_ALTERNATING
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reg r_a_last_owner;
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reg r_a_last_owner;
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// Stall must be asserted on the same cycle the input master asserts
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// the bus, if the bus isn't granted to him.
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assign o_a_stall = (w_a_owner) ? i_stall : 1'b1;
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assign o_b_stall = (w_b_owner) ? i_stall : 1'b1;
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`endif
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`endif
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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begin
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| Line 173... |
Line 169... |
// the master in question does not own the bus. Hence we force it
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// the master in question does not own the bus. Hence we force it
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// low if the particular master doesn't own the bus.
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// low if the particular master doesn't own the bus.
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assign o_a_ack = (w_a_owner) ? i_ack : 1'b0;
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assign o_a_ack = (w_a_owner) ? i_ack : 1'b0;
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assign o_b_ack = (w_b_owner) ? i_ack : 1'b0;
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assign o_b_ack = (w_b_owner) ? i_ack : 1'b0;
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// Stall must be asserted on the same cycle the input master asserts
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// the bus, if the bus isn't granted to him.
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assign o_a_stall = (w_a_owner) ? i_stall : 1'b1;
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assign o_b_stall = (w_b_owner) ? i_stall : 1'b1;
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//
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//
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//
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//
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assign o_a_err = (w_a_owner) ? i_err : 1'b0;
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assign o_a_err = (w_a_owner) ? i_err : 1'b0;
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assign o_b_err = (w_b_owner) ? i_err : 1'b0;
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assign o_b_err = (w_b_owner) ? i_err : 1'b0;
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