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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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`define WBA_ALTERNATING
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`define WBA_ALTERNATING
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module wbarbiter(i_clk, i_rst,
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module wbarbiter(i_clk, i_rst,
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// Bus A
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// Bus A
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i_a_adr, i_a_dat, i_a_we, i_a_stb, i_a_cyc, o_a_ack, o_a_stall,
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i_a_adr, i_a_dat, i_a_we, i_a_stb, i_a_cyc, o_a_ack, o_a_stall, o_a_err,
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// Bus B
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// Bus B
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i_b_adr, i_b_dat, i_b_we, i_b_stb, i_b_cyc, o_b_ack, o_b_stall,
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i_b_adr, i_b_dat, i_b_we, i_b_stb, i_b_cyc, o_b_ack, o_b_stall, o_b_err,
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// Both buses
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// Both buses
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o_adr, o_dat, o_we, o_stb, o_cyc, i_ack, i_stall);
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o_adr, o_dat, o_we, o_stb, o_cyc, i_ack, i_stall, i_err);
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// 18 bits will address one GB, 4 bytes at a time.
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// 18 bits will address one GB, 4 bytes at a time.
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// 19 bits will allow the ability to address things other than just
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// 19 bits will allow the ability to address things other than just
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// the 1GB of memory we are expecting.
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// the 1GB of memory we are expecting.
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parameter DW=32, AW=19;
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parameter DW=32, AW=19;
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// Wishbone doesn't use an i_ce signal. While it could, they dislike
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// Wishbone doesn't use an i_ce signal. While it could, they dislike
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input i_clk, i_rst;
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input i_clk, i_rst;
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input [(AW-1):0] i_a_adr, i_b_adr;
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input [(AW-1):0] i_a_adr, i_b_adr;
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input [(DW-1):0] i_a_dat, i_b_dat;
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input [(DW-1):0] i_a_dat, i_b_dat;
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input i_a_we, i_a_stb, i_a_cyc;
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input i_a_we, i_a_stb, i_a_cyc;
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input i_b_we, i_b_stb, i_b_cyc;
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input i_b_we, i_b_stb, i_b_cyc;
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output wire o_a_ack, o_b_ack, o_a_stall, o_b_stall;
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output wire o_a_ack, o_b_ack, o_a_stall, o_b_stall,
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o_a_err, o_b_err;
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output wire [(AW-1):0] o_adr;
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output wire [(AW-1):0] o_adr;
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output wire [(DW-1):0] o_dat;
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output wire [(DW-1):0] o_dat;
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output wire o_we, o_stb, o_cyc;
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output wire o_we, o_stb, o_cyc;
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input i_ack, i_stall;
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input i_ack, i_stall, i_err;
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// All the fancy stuff here is done with the three primary signals:
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// All the fancy stuff here is done with the three primary signals:
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// o_cyc
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// o_cyc
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// w_a_owner
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// w_a_owner
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// w_b_owner
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// w_b_owner
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// first clock of the bus cycle
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// first clock of the bus cycle
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reg r_a_owner, r_b_owner;
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reg r_a_owner, r_b_owner;
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wire w_a_owner, w_b_owner;
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wire w_a_owner, w_b_owner;
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`ifdef WBA_ALTERNATING
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`ifdef WBA_ALTERNATING
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reg r_a_last_owner;
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reg r_a_last_owner;
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// Stall must be asserted on the same cycle the input master asserts
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// the bus, if the bus isn't granted to him.
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assign o_a_stall = (w_a_owner) ? i_stall : 1'b1;
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assign o_b_stall = (w_b_owner) ? i_stall : 1'b1;
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`endif
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`endif
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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begin
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begin
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r_a_owner <= 1'b0;
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r_a_owner <= 1'b0;
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// the master in question does not own the bus. Hence we force it
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// the master in question does not own the bus. Hence we force it
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// low if the particular master doesn't own the bus.
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// low if the particular master doesn't own the bus.
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assign o_a_ack = (w_a_owner) ? i_ack : 1'b0;
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assign o_a_ack = (w_a_owner) ? i_ack : 1'b0;
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assign o_b_ack = (w_b_owner) ? i_ack : 1'b0;
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assign o_b_ack = (w_b_owner) ? i_ack : 1'b0;
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// Stall must be asserted on the same cycle the input master asserts
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//
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// the bus, if the bus isn't granted to him.
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//
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assign o_a_stall = (w_a_owner) ? i_stall : 1'b1;
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assign o_a_err = (w_a_owner) ? i_err : 1'b0;
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assign o_b_stall = (w_b_owner) ? i_stall : 1'b1;
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assign o_b_err = (w_b_owner) ? i_err : 1'b0;
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endmodule
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endmodule
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