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// http://www.gnu.org/licenses/gpl.html
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// http://www.gnu.org/licenses/gpl.html
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//
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//
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//
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//
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///////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////
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//
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//
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module wbpriarbiter(i_clk, i_rst,
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module wbpriarbiter(i_clk,
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// Bus A
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// Bus A
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i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err,
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i_a_cyc, i_a_stb, i_a_we, i_a_adr, i_a_dat, o_a_ack, o_a_stall, o_a_err,
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// Bus B
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// Bus B
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i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err,
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i_b_cyc, i_b_stb, i_b_we, i_b_adr, i_b_dat, o_b_ack, o_b_stall, o_b_err,
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// Both buses
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// Both buses
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o_cyc, o_stb, o_we, o_adr, o_dat, i_ack, i_stall, i_err);
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o_cyc, o_stb, o_we, o_adr, o_dat, i_ack, i_stall, i_err);
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parameter DW=32, AW=32;
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parameter DW=32, AW=32;
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// Wishbone doesn't use an i_ce signal. While it could, they dislike
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//
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// what it would (might) do to the synchronous reset signal, i_rst.
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input i_clk;
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input i_clk, i_rst;
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// Bus A
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// Bus A
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input i_a_cyc, i_a_stb, i_a_we;
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input i_a_cyc, i_a_stb, i_a_we;
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input [(AW-1):0] i_a_adr;
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input [(AW-1):0] i_a_adr;
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input [(DW-1):0] i_a_dat;
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input [(DW-1):0] i_a_dat;
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output wire o_a_ack, o_a_stall, o_a_err;
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output wire o_a_ack, o_a_stall, o_a_err;
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